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use MIPS_TLB_NB constant (Ralf Baechle) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1479 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2005-07-02 15:31:15 +00:00
parent e1d9a50836
commit 7a962d3087
2 changed files with 8 additions and 6 deletions
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2
target-mips/helper.c
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@ -33,7 +33,7 @@ static int map_address (CPUState *env, target_ulong *physical, int *prot,
ret = -2; ret = -2;
tag = (address & 0xFFFFE000); tag = (address & 0xFFFFE000);
ASID = env->CP0_EntryHi & 0x000000FF; ASID = env->CP0_EntryHi & 0x000000FF;
for (i = 0; i < 16; i++) { for (i = 0; i < MIPS_TLB_NB; i++) {
tlb = &env->tlb[i]; tlb = &env->tlb[i];
/* Check ASID, virtual page number & size */ /* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && if ((tlb->G == 1 || tlb->ASID == ASID) &&

12
target-mips/op_helper.c
View File

@ -531,8 +531,10 @@ static void fill_tb (int idx)
void do_tlbwi (void) void do_tlbwi (void)
{ {
invalidate_tb(env->CP0_index & 0xF); /* Wildly undefined effects for CP0_index containing a too high value and
fill_tb(env->CP0_index & 0xF); MIPS_TLB_NB not being a power of two. But so does real silicon. */
invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1));
fill_tb(env->CP0_index & (MIPS_TLB_NB - 1));
} }
void do_tlbwr (void) void do_tlbwr (void)
@ -552,7 +554,7 @@ void do_tlbp (void)
tag = (env->CP0_EntryHi & 0xFFFFE000); tag = (env->CP0_EntryHi & 0xFFFFE000);
ASID = env->CP0_EntryHi & 0x000000FF; ASID = env->CP0_EntryHi & 0x000000FF;
for (i = 0; i < 16; i++) { for (i = 0; i < MIPS_TLB_NB; i++) {
tlb = &env->tlb[i]; tlb = &env->tlb[i];
/* Check ASID, virtual page number & size */ /* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
@ -561,7 +563,7 @@ void do_tlbp (void)
break; break;
} }
} }
if (i == 16) { if (i == MIPS_TLB_NB) {
env->CP0_index |= 0x80000000; env->CP0_index |= 0x80000000;
} }
} }
@ -571,7 +573,7 @@ void do_tlbr (void)
tlb_t *tlb; tlb_t *tlb;
int size; int size;
tlb = &env->tlb[env->CP0_index & 0xF]; tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
env->CP0_EntryHi = tlb->VPN | tlb->ASID; env->CP0_EntryHi = tlb->VPN | tlb->ASID;
size = (tlb->end - tlb->VPN) >> 12; size = (tlb->end - tlb->VPN) >> 12;
env->CP0_PageMask = (size - 1) << 13; env->CP0_PageMask = (size - 1) << 13;