mirror of https://github.com/xqemu/xqemu.git
target-arm: Convert final ID registers
Convert the final ID registers to the new cp15 scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
81bdde9dcd
commit
7884849cc5
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@ -72,11 +72,9 @@ static void arm_cpu_reset(CPUState *s)
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
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env->cp15.c0_cpuid = cpu->midr;
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->cp15.c0_cachetype = cpu->ctr;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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@ -1003,6 +1003,74 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (arm_feature(env, ARM_FEATURE_MPIDR)) {
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if (arm_feature(env, ARM_FEATURE_MPIDR)) {
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define_arm_cp_regs(cpu, mpidr_cp_reginfo);
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define_arm_cp_regs(cpu, mpidr_cp_reginfo);
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}
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}
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/* Slightly awkwardly, the OMAP and StrongARM cores need all of
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* cp15 crn=0 to be writes-ignored, whereas for other cores they should
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* be read-only (ie write causes UNDEF exception).
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*/
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{
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ARMCPRegInfo id_cp_reginfo[] = {
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/* Note that the MIDR isn't a simple constant register because
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* of the TI925 behaviour where writes to another register can
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* cause the MIDR value to change.
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*/
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{ .name = "MIDR",
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_R, .resetvalue = cpu->midr,
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.writefn = arm_cp_write_ignore,
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.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
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{ .name = "CTR",
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
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{ .name = "TCMTR",
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "TLBTR",
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
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{ .name = "DUMMY",
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.cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "DUMMY",
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.cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "DUMMY",
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.cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "DUMMY",
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.cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "DUMMY",
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.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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ARMCPRegInfo crn0_wi_reginfo = {
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.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
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.type = ARM_CP_NOP | ARM_CP_OVERRIDE
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};
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if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
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arm_feature(env, ARM_FEATURE_STRONGARM)) {
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ARMCPRegInfo *r;
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/* Register the blanket "writes ignored" value first to cover the
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* whole space. Then define the specific ID registers, but update
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* their access field to allow write access, so that they ignore
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* writes rather than causing them to UNDEF.
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*/
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define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
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for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
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r->access = PL1_RW;
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define_one_arm_cp_reg(cpu, r);
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}
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} else {
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/* Just register the standard ID registers (read-only, meaning
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* that writes will UNDEF).
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*/
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define_arm_cp_regs(cpu, id_cp_reginfo);
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}
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}
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if (arm_feature(env, ARM_FEATURE_AUXCR)) {
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if (arm_feature(env, ARM_FEATURE_AUXCR)) {
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ARMCPRegInfo auxcr = {
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ARMCPRegInfo auxcr = {
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.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
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.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
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@ -2105,21 +2173,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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op1 = (insn >> 21) & 7;
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op1 = (insn >> 21) & 7;
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op2 = (insn >> 5) & 7;
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op2 = (insn >> 5) & 7;
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crm = insn & 0xf;
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crm = insn & 0xf;
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switch ((insn >> 16) & 0xf) {
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case 0:
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/* ID codes. */
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if (arm_feature(env, ARM_FEATURE_XSCALE))
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break;
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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break;
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goto bad_reg;
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case 4: /* Reserved. */
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goto bad_reg;
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case 12: /* Reserved. */
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goto bad_reg;
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}
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return;
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bad_reg:
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/* ??? For debugging only. Should raise illegal instruction exception. */
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/* ??? For debugging only. Should raise illegal instruction exception. */
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cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
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cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
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(insn >> 16) & 0xf, crm, op1, op2);
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(insn >> 16) & 0xf, crm, op1, op2);
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@ -2134,39 +2187,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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op1 = (insn >> 21) & 7;
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op1 = (insn >> 21) & 7;
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op2 = (insn >> 5) & 7;
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op2 = (insn >> 5) & 7;
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crm = insn & 0xf;
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crm = insn & 0xf;
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switch ((insn >> 16) & 0xf) {
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case 0: /* ID codes. */
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switch (op1) {
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case 0:
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switch (crm) {
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case 0:
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switch (op2) {
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case 0: /* Device ID. */
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return env->cp15.c0_cpuid;
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case 1: /* Cache Type. */
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return env->cp15.c0_cachetype;
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case 2: /* TCM status. */
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return 0;
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case 3: /* TLB type register. */
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return 0; /* No lockable TLB entries. */
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default:
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goto bad_reg;
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}
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case 3: case 4: case 5: case 6: case 7:
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return 0;
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default:
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goto bad_reg;
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}
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default:
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goto bad_reg;
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}
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case 4: /* Reserved. */
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goto bad_reg;
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case 11: /* TCM DMA control. */
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case 12: /* Reserved. */
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goto bad_reg;
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}
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bad_reg:
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/* ??? For debugging only. Should raise illegal instruction exception. */
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/* ??? For debugging only. Should raise illegal instruction exception. */
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cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
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cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
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(insn >> 16) & 0xf, crm, op1, op2);
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(insn >> 16) & 0xf, crm, op1, op2);
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