mirror of https://github.com/xqemu/xqemu.git
cadence_gem: Correct indentation
Fix up the indentation inside the for loop that was introduced in the previous patch. This commit is almost empty if viewed using 'git show -w', except for a few changes that were required to avoid the 80 charecter line limit. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: b40d1b12d24be9f0ac5d72f86249103e0c1c720a.1469727764.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alistair Francis
Peter Maydell
parent
6710172501
commit
77524d1157
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@ -1054,117 +1054,122 @@ static void gem_transmit(CadenceGEMState *s)
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total_bytes = 0;
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total_bytes = 0;
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for (q = s->num_priority_queues - 1; q >= 0; q--) {
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for (q = s->num_priority_queues - 1; q >= 0; q--) {
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/* read current descriptor */
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/* read current descriptor */
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packet_desc_addr = s->tx_desc_addr[q];
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packet_desc_addr = s->tx_desc_addr[q];
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DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
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cpu_physical_memory_read(packet_desc_addr,
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(uint8_t *)desc, sizeof(desc));
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/* Handle all descriptors owned by hardware */
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while (tx_desc_get_used(desc) == 0) {
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/* Do nothing if transmit is not enabled. */
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if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
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return;
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}
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print_gem_tx_desc(desc, q);
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/* The real hardware would eat this (and possibly crash).
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* For QEMU let's lend a helping hand.
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*/
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if ((tx_desc_get_buffer(desc) == 0) ||
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(tx_desc_get_length(desc) == 0)) {
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DB_PRINT("Invalid TX descriptor @ 0x%x\n",
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(unsigned)packet_desc_addr);
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break;
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}
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if (tx_desc_get_length(desc) > sizeof(tx_packet) - (p - tx_packet)) {
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DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space 0x%x\n",
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(unsigned)packet_desc_addr,
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(unsigned)tx_desc_get_length(desc),
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sizeof(tx_packet) - (p - tx_packet));
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break;
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}
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/* Gather this fragment of the packet from "dma memory" to our contig.
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* buffer.
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*/
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cpu_physical_memory_read(tx_desc_get_buffer(desc), p,
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tx_desc_get_length(desc));
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p += tx_desc_get_length(desc);
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total_bytes += tx_desc_get_length(desc);
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/* Last descriptor for this packet; hand the whole thing off */
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if (tx_desc_get_last(desc)) {
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unsigned desc_first[2];
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/* Modify the 1st descriptor of this packet to be owned by
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* the processor.
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*/
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cpu_physical_memory_read(s->tx_desc_addr[q], (uint8_t *)desc_first,
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sizeof(desc_first));
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tx_desc_set_used(desc_first);
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cpu_physical_memory_write(s->tx_desc_addr[q], (uint8_t *)desc_first,
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sizeof(desc_first));
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/* Advance the hardware current descriptor past this packet */
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if (tx_desc_get_wrap(desc)) {
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s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
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} else {
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s->tx_desc_addr[q] = packet_desc_addr + 8;
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}
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DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
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s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
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s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
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/* Update queue interrupt status */
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if (s->num_priority_queues > 1) {
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s->regs[GEM_INT_Q1_STATUS + q] |=
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GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
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}
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/* Handle interrupt consequences */
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gem_update_int_status(s);
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/* Is checksum offload enabled? */
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if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
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net_checksum_calculate(tx_packet, total_bytes);
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}
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/* Update MAC statistics */
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gem_transmit_updatestats(s, tx_packet, total_bytes);
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/* Send the packet somewhere */
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if (s->phy_loop || (s->regs[GEM_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) {
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gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes);
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} else {
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qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
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total_bytes);
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}
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/* Prepare for next packet */
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p = tx_packet;
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total_bytes = 0;
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}
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/* read next descriptor */
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if (tx_desc_get_wrap(desc)) {
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tx_desc_set_last(desc);
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packet_desc_addr = s->regs[GEM_TXQBASE];
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} else {
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packet_desc_addr += 8;
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}
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DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
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DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
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cpu_physical_memory_read(packet_desc_addr,
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cpu_physical_memory_read(packet_desc_addr,
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(uint8_t *)desc, sizeof(desc));
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(uint8_t *)desc, sizeof(desc));
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}
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/* Handle all descriptors owned by hardware */
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while (tx_desc_get_used(desc) == 0) {
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if (tx_desc_get_used(desc)) {
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/* Do nothing if transmit is not enabled. */
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s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
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if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
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s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
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return;
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gem_update_int_status(s);
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}
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}
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print_gem_tx_desc(desc, q);
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/* The real hardware would eat this (and possibly crash).
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* For QEMU let's lend a helping hand.
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*/
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if ((tx_desc_get_buffer(desc) == 0) ||
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(tx_desc_get_length(desc) == 0)) {
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DB_PRINT("Invalid TX descriptor @ 0x%x\n",
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(unsigned)packet_desc_addr);
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break;
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}
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if (tx_desc_get_length(desc) > sizeof(tx_packet) -
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(p - tx_packet)) {
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DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
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"0x%x\n", (unsigned)packet_desc_addr,
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(unsigned)tx_desc_get_length(desc),
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sizeof(tx_packet) - (p - tx_packet));
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break;
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}
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/* Gather this fragment of the packet from "dma memory" to our
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* contig buffer.
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*/
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cpu_physical_memory_read(tx_desc_get_buffer(desc), p,
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tx_desc_get_length(desc));
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p += tx_desc_get_length(desc);
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total_bytes += tx_desc_get_length(desc);
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/* Last descriptor for this packet; hand the whole thing off */
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if (tx_desc_get_last(desc)) {
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unsigned desc_first[2];
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/* Modify the 1st descriptor of this packet to be owned by
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* the processor.
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*/
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cpu_physical_memory_read(s->tx_desc_addr[q],
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(uint8_t *)desc_first,
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sizeof(desc_first));
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tx_desc_set_used(desc_first);
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cpu_physical_memory_write(s->tx_desc_addr[q],
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(uint8_t *)desc_first,
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sizeof(desc_first));
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/* Advance the hardware current descriptor past this packet */
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if (tx_desc_get_wrap(desc)) {
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s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
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} else {
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s->tx_desc_addr[q] = packet_desc_addr + 8;
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}
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DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
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s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
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s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
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/* Update queue interrupt status */
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if (s->num_priority_queues > 1) {
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s->regs[GEM_INT_Q1_STATUS + q] |=
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GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
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}
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/* Handle interrupt consequences */
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gem_update_int_status(s);
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/* Is checksum offload enabled? */
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if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
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net_checksum_calculate(tx_packet, total_bytes);
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}
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/* Update MAC statistics */
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gem_transmit_updatestats(s, tx_packet, total_bytes);
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/* Send the packet somewhere */
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if (s->phy_loop || (s->regs[GEM_NWCTRL] &
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GEM_NWCTRL_LOCALLOOP)) {
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gem_receive(qemu_get_queue(s->nic), tx_packet,
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total_bytes);
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} else {
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qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
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total_bytes);
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}
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/* Prepare for next packet */
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p = tx_packet;
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total_bytes = 0;
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}
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/* read next descriptor */
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if (tx_desc_get_wrap(desc)) {
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tx_desc_set_last(desc);
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packet_desc_addr = s->regs[GEM_TXQBASE];
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} else {
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packet_desc_addr += 8;
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}
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DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
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cpu_physical_memory_read(packet_desc_addr,
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(uint8_t *)desc, sizeof(desc));
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}
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if (tx_desc_get_used(desc)) {
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s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
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s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
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gem_update_int_status(s);
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}
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}
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}
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}
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}
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