mirror of https://github.com/xqemu/xqemu.git
mmu-hash32: Split direct store segment handling into a helper
This further separates the unusual case handling of direct store segments from the main translation path by moving its logic into a helper function, with some tiny cleanups along the way. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
4b9605a5b1
commit
723ed73ada
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@ -243,6 +243,62 @@ static int ppc_hash32_get_bat(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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return ret;
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return ret;
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}
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}
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static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
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target_ulong eaddr, int rwx,
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hwaddr *raddr, int *prot)
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{
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int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
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LOG_MMU("direct store...\n");
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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*raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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if (rwx == 2) {
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/* No code fetch is allowed in direct-store areas */
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return -4;
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}
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switch (env->access_type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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return -4;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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return -4;
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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*raddr = eaddr;
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return 0;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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return -4;
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default:
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qemu_log("ERROR: instruction should not need "
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"address translation\n");
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return -4;
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}
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if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
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*raddr = eaddr;
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return 2;
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} else {
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return -2;
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}
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}
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static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0,
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static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rwx)
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target_ulong pte1, int h, int rwx)
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{
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{
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@ -404,66 +460,15 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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/* 3. Look up the Segment Register */
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/* 3. Look up the Segment Register */
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sr = env->sr[eaddr >> 28];
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sr = env->sr[eaddr >> 28];
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/* 4. Handle direct store segments */
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if (sr & SR32_T) {
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return ppc_hash32_direct_store(env, sr, eaddr, rwx,
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&ctx->raddr, &ctx->prot);
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}
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pr = msr_pr;
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pr = msr_pr;
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ctx->key = (((sr & SR32_KP) && (pr != 0)) ||
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ctx->key = (((sr & SR32_KP) && (pr != 0)) ||
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((sr & SR32_KS) && (pr == 0))) ? 1 : 0;
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((sr & SR32_KS) && (pr == 0))) ? 1 : 0;
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/* 4. Handle direct store segments */
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if (sr & SR32_T) {
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LOG_MMU("direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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/* Direct-store implies a 32-bit MMU.
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* Check the Segment Register's bus unit ID (BUID).
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*/
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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if (rwx == 2) {
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/* No code fetch is allowed in direct-store areas */
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return -4;
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}
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switch (env->access_type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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return -4;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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return -4;
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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ctx->raddr = eaddr;
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return 0;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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return -4;
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default:
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qemu_log("ERROR: instruction should not need "
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"address translation\n");
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return -4;
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}
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if ((rwx == 1 || ctx->key != 1) && (rwx == 0 || ctx->key != 0)) {
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ctx->raddr = eaddr;
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return 2;
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} else {
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return -2;
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}
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}
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ctx->nx = !!(sr & SR32_NX);
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ctx->nx = !!(sr & SR32_NX);
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vsid = sr & SR32_VSID;
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vsid = sr & SR32_VSID;
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target_page_bits = TARGET_PAGE_BITS;
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target_page_bits = TARGET_PAGE_BITS;
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