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target-microblaze: Convert pvr-full to a CPU property 

Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Alistair Francis 2015-06-18 21:16:42 -07:00 committed by Edgar E. Iglesias
parent 72e3875485
commit 6fad9e986b
4 changed files with 10 additions and 6 deletions
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1
target-microblaze/cpu-qom.h
View File

@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
bool dcache_writeback; bool dcache_writeback;
bool endi; bool endi;
char *version; char *version;
uint8_t pvr;
} cfg; } cfg;
CPUMBState env; CPUMBState env;

7
target-microblaze/cpu.c
View File

@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
qemu_init_vcpu(cs); qemu_init_vcpu(cs);
env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
| PVR0_USE_BARREL_MASK \
| PVR0_USE_DIV_MASK \ | PVR0_USE_DIV_MASK \
| PVR0_USE_HW_MUL_MASK \ | PVR0_USE_HW_MUL_MASK \
| PVR0_USE_EXC_MASK \ | PVR0_USE_EXC_MASK \
@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
(version_code << 16); (version_code << 16) |
(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@ -228,6 +228,7 @@ static Property mb_properties[] = {
false), false),
DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

4
target-microblaze/cpu.h
View File

@ -212,7 +212,9 @@ typedef struct CPUMBState CPUMBState;
/* MSR Reset value PVR mask */ /* MSR Reset value PVR mask */
#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
#define C_PVR_NONE 0
#define C_PVR_BASIC 1
#define C_PVR_FULL 2
/* CPU flags. */ /* CPU flags. */

4
target-microblaze/helper.c
View File

@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
mmu_available = 0; mmu_available = 0;
if (cpu->cfg.use_mmu) { if (cpu->cfg.use_mmu) {
mmu_available = 1; mmu_available = 1;
if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK) if ((cpu->cfg.pvr == C_PVR_FULL) &&
&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
mmu_available = 0; mmu_available = 0;
} }
} }