mirror of https://github.com/xqemu/xqemu.git
target-sparc: Tidy save_state interface
Use the cpu_cond global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson
Blue Swirl
parent
5b12f1e8a1
commit
66442b07ae
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@ -1136,7 +1136,7 @@ static inline void save_npc(DisasContext *dc, TCGv cond)
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}
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}
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static inline void save_state(DisasContext *dc, TCGv cond)
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static inline void save_state(DisasContext *dc)
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{
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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/* flush pending conditional evaluations before exposing cpu state */
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@ -1144,7 +1144,7 @@ static inline void save_state(DisasContext *dc, TCGv cond)
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dc->cc_op = CC_OP_FLAGS;
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gen_helper_compute_psr(cpu_env);
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}
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save_npc(dc, cond);
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save_npc(dc, cpu_cond);
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}
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static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
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@ -1621,7 +1621,7 @@ static int gen_trap_ifnofpu(DisasContext *dc)
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if (!dc->fpu_enabled) {
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TCGv_i32 r_const;
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save_state(dc, cpu_cond);
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save_state(dc);
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r_const = tcg_const_i32(TT_NFPU_INSN);
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gen_helper_raise_exception(cpu_env, r_const);
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tcg_temp_free_i32(r_const);
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@ -2529,7 +2529,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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cond = GET_FIELD(insn, 3, 6);
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if (cond == 0x8) { /* Trap Always */
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save_state(dc, cpu_cond);
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save_state(dc);
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if ((dc->def->features & CPU_FEATURE_HYPV) &&
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supervisor(dc))
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tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
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@ -2546,7 +2546,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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/* V9 icc/xcc */
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int cc = GET_FIELD_SP(insn, 11, 12);
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save_state(dc, cpu_cond);
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save_state(dc);
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if (cc == 0)
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gen_cond(r_cond, 0, cond, dc);
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else if (cc == 2)
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@ -2554,7 +2554,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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else
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goto illegal_insn;
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#else
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_cond(r_cond, 0, cond, dc);
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#endif
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l1 = gen_new_label();
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@ -2854,7 +2854,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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break;
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} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
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#ifdef TARGET_SPARC64
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_helper_flushw(cpu_env);
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#else
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if (!supervisor(dc))
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@ -2871,7 +2871,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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rs1 = GET_FIELD(insn, 13, 17);
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rs2 = GET_FIELD(insn, 27, 31);
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xop = GET_FIELD(insn, 18, 26);
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save_state(dc, cpu_cond);
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save_state(dc);
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switch (xop) {
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case 0x1: /* fmovs */
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cpu_src1_32 = gen_load_fpr_F(dc, rs2);
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@ -3046,7 +3046,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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rs1 = GET_FIELD(insn, 13, 17);
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rs2 = GET_FIELD(insn, 27, 31);
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xop = GET_FIELD(insn, 18, 26);
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save_state(dc, cpu_cond);
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save_state(dc);
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#ifdef TARGET_SPARC64
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if ((xop & 0x11f) == 0x005) { // V9 fmovsr
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int l1;
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@ -3607,14 +3607,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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dc->cc_op = CC_OP_TSUB;
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break;
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case 0x22: /* taddcctv */
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
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gen_movl_TN_reg(rd, cpu_dst);
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tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV);
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dc->cc_op = CC_OP_TADDTV;
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break;
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case 0x23: /* tsubcctv */
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
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gen_movl_TN_reg(rd, cpu_dst);
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tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV);
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@ -3691,7 +3691,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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case 0x6: /* V9 wrfprs */
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tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
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tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst);
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_op_next_insn();
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tcg_gen_exit_tb(0);
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dc->is_br = 1;
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@ -3818,7 +3818,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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gen_helper_wrpsr(cpu_env, cpu_dst);
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tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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dc->cc_op = CC_OP_FLAGS;
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_op_next_insn();
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tcg_gen_exit_tb(0);
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dc->is_br = 1;
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@ -3898,7 +3898,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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TCGv r_tmp = tcg_temp_local_new();
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tcg_gen_mov_tl(r_tmp, cpu_tmp0);
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_helper_wrpstate(cpu_env, r_tmp);
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tcg_temp_free(r_tmp);
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dc->npc = DYNAMIC_PC;
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@ -3909,7 +3909,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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TCGv r_tmp = tcg_temp_local_new();
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tcg_gen_mov_tl(r_tmp, cpu_tmp0);
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save_state(dc, cpu_cond);
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save_state(dc);
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tcg_gen_trunc_tl_i32(cpu_tmp32, r_tmp);
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tcg_temp_free(r_tmp);
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tcg_gen_st_i32(cpu_tmp32, cpu_env,
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@ -3991,7 +3991,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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switch (rd) {
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case 0: // hpstate
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// XXX gen_op_wrhpstate();
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_op_next_insn();
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tcg_gen_exit_tb(0);
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dc->is_br = 1;
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@ -4559,7 +4559,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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} else if (xop == 0x39) { /* V9 return */
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TCGv_i32 r_const;
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save_state(dc, cpu_cond);
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save_state(dc);
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cpu_src1 = get_src1(insn, cpu_src1);
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if (IS_IMM) { /* immediate */
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simm = GET_FIELDs(insn, 19, 31);
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@ -4635,12 +4635,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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/* nop */
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break;
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case 0x3c: /* save */
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_helper_save(cpu_env);
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gen_movl_TN_reg(rd, cpu_dst);
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break;
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case 0x3d: /* restore */
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_helper_restore(cpu_env);
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gen_movl_TN_reg(rd, cpu_dst);
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break;
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@ -4723,7 +4723,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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else {
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TCGv_i32 r_const;
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save_state(dc, cpu_cond);
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save_state(dc);
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r_const = tcg_const_i32(7);
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/* XXX remove alignment check */
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gen_helper_check_align(cpu_env, cpu_addr, r_const);
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@ -4774,7 +4774,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
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break;
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case 0x11: /* lduba, load unsigned byte alternate */
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@ -4784,7 +4784,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
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break;
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case 0x12: /* lduha, load unsigned halfword alternate */
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@ -4794,7 +4794,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
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break;
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case 0x13: /* ldda, load double word alternate */
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@ -4806,7 +4806,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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#endif
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if (rd & 1)
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goto illegal_insn;
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
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goto skip_move;
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case 0x19: /* ldsba, load signed byte alternate */
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@ -4816,7 +4816,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
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break;
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case 0x1a: /* ldsha, load signed halfword alternate */
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@ -4826,7 +4826,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
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break;
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case 0x1d: /* ldstuba -- XXX: should be atomically */
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@ -4836,7 +4836,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ldstub_asi(cpu_val, cpu_addr, insn);
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break;
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case 0x1f: /* swapa, swap reg with alt. memory. Also
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@ -4848,7 +4848,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_movl_reg_TN(rd, cpu_val);
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gen_swap_asi(cpu_val, cpu_addr, insn);
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break;
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@ -4870,11 +4870,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x18: /* V9 ldswa */
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
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break;
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case 0x1b: /* V9 ldxa */
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
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break;
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case 0x2d: /* V9 prefetch, no effect */
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@ -4883,7 +4883,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (gen_trap_ifnofpu(dc)) {
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goto jmp_insn;
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}
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ldf_asi(cpu_addr, insn, 4, rd);
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gen_update_fprs_dirty(rd);
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goto skip_move;
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@ -4891,7 +4891,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (gen_trap_ifnofpu(dc)) {
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goto jmp_insn;
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}
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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goto skip_move;
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@ -4902,7 +4902,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (gen_trap_ifnofpu(dc)) {
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goto jmp_insn;
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}
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
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gen_update_fprs_dirty(QFPREG(rd));
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goto skip_move;
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@ -4918,7 +4918,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (gen_trap_ifnofpu(dc)) {
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goto jmp_insn;
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}
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save_state(dc, cpu_cond);
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save_state(dc);
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switch (xop) {
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case 0x20: /* ldf, load fpreg */
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gen_address_mask(dc, cpu_addr);
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@ -4989,7 +4989,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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else {
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TCGv_i32 r_const;
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_address_mask(dc, cpu_addr);
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r_const = tcg_const_i32(7);
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/* XXX remove alignment check */
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@ -5008,7 +5008,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_st_asi(cpu_val, cpu_addr, insn, 4);
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dc->npc = DYNAMIC_PC;
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break;
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@ -5019,7 +5019,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_st_asi(cpu_val, cpu_addr, insn, 1);
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dc->npc = DYNAMIC_PC;
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break;
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@ -5030,7 +5030,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (!supervisor(dc))
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goto priv_insn;
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#endif
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_st_asi(cpu_val, cpu_addr, insn, 2);
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dc->npc = DYNAMIC_PC;
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break;
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@ -5044,7 +5044,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (rd & 1)
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goto illegal_insn;
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else {
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_stda_asi(cpu_val, cpu_addr, insn, rd);
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}
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break;
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@ -5055,7 +5055,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x1e: /* V9 stxa */
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save_state(dc, cpu_cond);
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save_state(dc);
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gen_st_asi(cpu_val, cpu_addr, insn, 8);
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dc->npc = DYNAMIC_PC;
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break;
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@ -5067,7 +5067,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (gen_trap_ifnofpu(dc)) {
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goto jmp_insn;
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}
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save_state(dc, cpu_cond);
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save_state(dc);
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switch (xop) {
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case 0x24: /* stf, store fpreg */
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gen_address_mask(dc, cpu_addr);
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@ -5124,7 +5124,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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goto illegal_insn;
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}
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} else if (xop > 0x33 && xop < 0x3f) {
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save_state(dc, cpu_cond);
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save_state(dc);
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switch (xop) {
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#ifdef TARGET_SPARC64
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case 0x34: /* V9 stfa */
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@ -5194,7 +5194,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
|
|||
{
|
||||
TCGv_i32 r_const;
|
||||
|
||||
save_state(dc, cpu_cond);
|
||||
save_state(dc);
|
||||
r_const = tcg_const_i32(TT_ILL_INSN);
|
||||
gen_helper_raise_exception(cpu_env, r_const);
|
||||
tcg_temp_free_i32(r_const);
|
||||
|
|
@ -5205,7 +5205,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
|
|||
{
|
||||
TCGv_i32 r_const;
|
||||
|
||||
save_state(dc, cpu_cond);
|
||||
save_state(dc);
|
||||
r_const = tcg_const_i32(TT_UNIMP_FLUSH);
|
||||
gen_helper_raise_exception(cpu_env, r_const);
|
||||
tcg_temp_free_i32(r_const);
|
||||
|
|
@ -5217,7 +5217,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
|
|||
{
|
||||
TCGv_i32 r_const;
|
||||
|
||||
save_state(dc, cpu_cond);
|
||||
save_state(dc);
|
||||
r_const = tcg_const_i32(TT_PRIV_INSN);
|
||||
gen_helper_raise_exception(cpu_env, r_const);
|
||||
tcg_temp_free_i32(r_const);
|
||||
|
|
@ -5226,13 +5226,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
|
|||
goto egress;
|
||||
#endif
|
||||
nfpu_insn:
|
||||
save_state(dc, cpu_cond);
|
||||
save_state(dc);
|
||||
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
|
||||
dc->is_br = 1;
|
||||
goto egress;
|
||||
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
||||
nfq_insn:
|
||||
save_state(dc, cpu_cond);
|
||||
save_state(dc);
|
||||
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
|
||||
dc->is_br = 1;
|
||||
goto egress;
|
||||
|
|
@ -5242,7 +5242,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
|
|||
{
|
||||
TCGv r_const;
|
||||
|
||||
save_state(dc, cpu_cond);
|
||||
save_state(dc);
|
||||
r_const = tcg_const_i32(TT_NCP_INSN);
|
||||
gen_helper_raise_exception(cpu_env, r_const);
|
||||
tcg_temp_free(r_const);
|
||||
|
|
@ -5308,7 +5308,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
|
|||
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
||||
if (bp->pc == dc->pc) {
|
||||
if (dc->pc != pc_start)
|
||||
save_state(dc, cpu_cond);
|
||||
save_state(dc);
|
||||
gen_helper_debug(cpu_env);
|
||||
tcg_gen_exit_tb(0);
|
||||
dc->is_br = 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue