mirror of https://github.com/xqemu/xqemu.git
sm501: Fixed code style and a few typos in comments
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 36288b703e7d56822c818567193ff28cdc47377e.1492787889.git.balaton@eik.bme.hu Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
BALATON Zoltan
Peter Maydell
parent
d526e5d874
commit
64f1603b07
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@ -38,7 +38,7 @@
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/*
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* Status: 2010/05/07
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* - Minimum implementation for Linux console : mmio regs and CRT layer.
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* - 2D grapihcs acceleration partially supported : only fill rectangle.
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* - 2D graphics acceleration partially supported : only fill rectangle.
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*
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* TODO:
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* - Panel support
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@ -49,13 +49,13 @@
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* - Performance tuning
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*/
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//#define DEBUG_SM501
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//#define DEBUG_BITBLT
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/*#define DEBUG_SM501*/
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/*#define DEBUG_BITBLT*/
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#ifdef DEBUG_SM501
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#define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
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#else
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#define SM501_DPRINTF(fmt, ...) do {} while(0)
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#define SM501_DPRINTF(fmt, ...) do {} while (0)
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#endif
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@ -70,20 +70,20 @@
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/* config 1 */
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#define SM501_SYSTEM_CONTROL (0x000000)
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#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
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#define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
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#define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
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#define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
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#define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
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#define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
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#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
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#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
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#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
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#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
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#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
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#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
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#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
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#define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
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/* miscellaneous control */
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@ -95,26 +95,26 @@
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#define SM501_MISC_BUS_NEC (0x6)
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#define SM501_MISC_BUS_MASK (0x7)
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#define SM501_MISC_VR_62MB (1<<3)
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#define SM501_MISC_CDR_RESET (1<<7)
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#define SM501_MISC_USB_LB (1<<8)
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#define SM501_MISC_USB_SLAVE (1<<9)
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#define SM501_MISC_BL_1 (1<<10)
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#define SM501_MISC_MC (1<<11)
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#define SM501_MISC_DAC_POWER (1<<12)
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#define SM501_MISC_IRQ_INVERT (1<<16)
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#define SM501_MISC_SH (1<<17)
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#define SM501_MISC_VR_62MB (1 << 3)
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#define SM501_MISC_CDR_RESET (1 << 7)
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#define SM501_MISC_USB_LB (1 << 8)
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#define SM501_MISC_USB_SLAVE (1 << 9)
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#define SM501_MISC_BL_1 (1 << 10)
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#define SM501_MISC_MC (1 << 11)
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#define SM501_MISC_DAC_POWER (1 << 12)
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#define SM501_MISC_IRQ_INVERT (1 << 16)
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#define SM501_MISC_SH (1 << 17)
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#define SM501_MISC_HOLD_EMPTY (0<<18)
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#define SM501_MISC_HOLD_8 (1<<18)
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#define SM501_MISC_HOLD_16 (2<<18)
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#define SM501_MISC_HOLD_24 (3<<18)
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#define SM501_MISC_HOLD_32 (4<<18)
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#define SM501_MISC_HOLD_MASK (7<<18)
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#define SM501_MISC_HOLD_EMPTY (0 << 18)
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#define SM501_MISC_HOLD_8 (1 << 18)
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#define SM501_MISC_HOLD_16 (2 << 18)
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#define SM501_MISC_HOLD_24 (3 << 18)
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#define SM501_MISC_HOLD_32 (4 << 18)
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#define SM501_MISC_HOLD_MASK (7 << 18)
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#define SM501_MISC_FREQ_12 (1<<24)
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#define SM501_MISC_PNL_24BIT (1<<25)
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#define SM501_MISC_8051_LE (1<<26)
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#define SM501_MISC_FREQ_12 (1 << 24)
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#define SM501_MISC_PNL_24BIT (1 << 25)
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#define SM501_MISC_8051_LE (1 << 26)
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@ -136,10 +136,10 @@
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#define SM501_DEBUG_CONTROL (0x000034)
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/* power management */
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#define SM501_POWERMODE_P2X_SRC (1<<29)
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#define SM501_POWERMODE_V2X_SRC (1<<20)
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#define SM501_POWERMODE_M_SRC (1<<12)
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#define SM501_POWERMODE_M1_SRC (1<<4)
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#define SM501_POWERMODE_P2X_SRC (1 << 29)
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#define SM501_POWERMODE_V2X_SRC (1 << 20)
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#define SM501_POWERMODE_M_SRC (1 << 12)
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#define SM501_POWERMODE_M1_SRC (1 << 4)
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#define SM501_CURRENT_GATE (0x000038)
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#define SM501_CURRENT_CLOCK (0x00003C)
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@ -232,9 +232,9 @@
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#define SM501_DC (0x080000)
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/* common defines for the SM501 address registers */
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#define SM501_ADDR_FLIP (1<<31)
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#define SM501_ADDR_EXT (1<<27)
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#define SM501_ADDR_CS1 (1<<26)
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#define SM501_ADDR_FLIP (1 << 31)
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#define SM501_ADDR_EXT (1 << 27)
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#define SM501_ADDR_CS1 (1 << 26)
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#define SM501_ADDR_MASK (0x3f << 26)
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#define SM501_FIFO_MASK (0x3 << 16)
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@ -251,37 +251,37 @@
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#define SM501_DC_PANEL_CONTROL (0x000)
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#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
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#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
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#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
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#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
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#define SM501_DC_PANEL_CONTROL_DP (1<<23)
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#define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
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#define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
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#define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
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#define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
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#define SM501_DC_PANEL_CONTROL_DP (1 << 23)
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#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
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#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
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#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
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#define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
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#define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
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#define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
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#define SM501_DC_PANEL_CONTROL_DE (1<<20)
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#define SM501_DC_PANEL_CONTROL_DE (1 << 20)
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#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
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#define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
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#define SM501_DC_PANEL_CONTROL_CP (1<<14)
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#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
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#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
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#define SM501_DC_PANEL_CONTROL_CK (1<<9)
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#define SM501_DC_PANEL_CONTROL_TE (1<<8)
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#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
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#define SM501_DC_PANEL_CONTROL_VP (1<<6)
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#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
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#define SM501_DC_PANEL_CONTROL_HP (1<<4)
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#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
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#define SM501_DC_PANEL_CONTROL_EN (1<<2)
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#define SM501_DC_PANEL_CONTROL_CP (1 << 14)
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#define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
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#define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
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#define SM501_DC_PANEL_CONTROL_CK (1 << 9)
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#define SM501_DC_PANEL_CONTROL_TE (1 << 8)
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#define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
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#define SM501_DC_PANEL_CONTROL_VP (1 << 6)
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#define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
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#define SM501_DC_PANEL_CONTROL_HP (1 << 4)
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#define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
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#define SM501_DC_PANEL_CONTROL_EN (1 << 2)
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#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
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#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
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#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
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#define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
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#define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
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#define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
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#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
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@ -327,7 +327,7 @@
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#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
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#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
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#define SM501_HWC_EN (1<<31)
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#define SM501_HWC_EN (1 << 31)
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#define SM501_OFF_HWC_ADDR (0x00)
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#define SM501_OFF_HWC_LOC (0x04)
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@ -344,21 +344,21 @@
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#define SM501_DC_CRT_CONTROL (0x200)
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#define SM501_DC_CRT_CONTROL_TVP (1<<15)
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#define SM501_DC_CRT_CONTROL_CP (1<<14)
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#define SM501_DC_CRT_CONTROL_VSP (1<<13)
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#define SM501_DC_CRT_CONTROL_HSP (1<<12)
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#define SM501_DC_CRT_CONTROL_VS (1<<11)
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#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
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#define SM501_DC_CRT_CONTROL_SEL (1<<9)
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#define SM501_DC_CRT_CONTROL_TE (1<<8)
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#define SM501_DC_CRT_CONTROL_TVP (1 << 15)
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#define SM501_DC_CRT_CONTROL_CP (1 << 14)
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#define SM501_DC_CRT_CONTROL_VSP (1 << 13)
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#define SM501_DC_CRT_CONTROL_HSP (1 << 12)
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#define SM501_DC_CRT_CONTROL_VS (1 << 11)
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#define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
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#define SM501_DC_CRT_CONTROL_SEL (1 << 9)
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#define SM501_DC_CRT_CONTROL_TE (1 << 8)
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#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
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#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
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#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
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#define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
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#define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
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#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
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#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
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#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
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#define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
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#define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
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#define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
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#define SM501_DC_CRT_FB_ADDR (0x204)
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#define SM501_DC_CRT_FB_OFFSET (0x208)
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@ -446,12 +446,12 @@
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/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
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static const uint32_t sm501_mem_local_size[] = {
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[0] = 4*1024*1024,
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[1] = 8*1024*1024,
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[2] = 16*1024*1024,
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[3] = 32*1024*1024,
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[4] = 64*1024*1024,
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[5] = 2*1024*1024,
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[0] = 4 * 1024 * 1024,
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[1] = 8 * 1024 * 1024,
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[2] = 16 * 1024 * 1024,
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[3] = 32 * 1024 * 1024,
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[4] = 64 * 1024 * 1024,
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[5] = 2 * 1024 * 1024,
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};
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#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
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@ -462,7 +462,7 @@ typedef struct SM501State {
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/* status & internal resources */
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hwaddr base;
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uint32_t local_mem_size_index;
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uint8_t * local_mem;
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uint8_t *local_mem;
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MemoryRegion local_mem_region;
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uint32_t last_width;
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uint32_t last_height;
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@ -637,7 +637,7 @@ static int within_hwc_y_range(SM501State *state, int y, int crt)
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return (hwc_y <= y && y < hwc_y + SM501_HWC_HEIGHT);
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}
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static void sm501_2d_operation(SM501State * s)
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static void sm501_2d_operation(SM501State *s)
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{
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/* obtain operation parameters */
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int operation = (s->twoD_control >> 16) & 0x1f;
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@ -653,8 +653,8 @@ static void sm501_2d_operation(SM501State * s)
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int addressing = (s->twoD_stretch >> 16) & 0xF;
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/* get frame buffer info */
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uint8_t * src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
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uint8_t * dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
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uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
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uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
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int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
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int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
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@ -682,7 +682,7 @@ static void sm501_2d_operation(SM501State * s)
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index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
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index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
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} \
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*(_pixel_type*)&dst[index_d] = *(_pixel_type*)&src[index_s];\
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*(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\
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} \
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} \
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}
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@ -705,7 +705,7 @@ static void sm501_2d_operation(SM501State * s)
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for (y = 0; y < operation_height; y++) { \
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for (x = 0; x < operation_width; x++) { \
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int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
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*(_pixel_type*)&dst[index] = (_pixel_type)color; \
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*(_pixel_type *)&dst[index] = (_pixel_type)color; \
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} \
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} \
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}
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@ -733,11 +733,11 @@ static void sm501_2d_operation(SM501State * s)
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static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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SM501State * s = (SM501State *)opaque;
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SM501State *s = (SM501State *)opaque;
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uint32_t ret = 0;
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SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
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switch(addr) {
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switch (addr) {
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case SM501_SYSTEM_CONTROL:
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ret = s->system_control;
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break;
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@ -786,11 +786,11 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
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static void sm501_system_config_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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SM501State * s = (SM501State *)opaque;
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SM501State *s = (SM501State *)opaque;
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SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
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(uint32_t)addr, (uint32_t)value);
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switch(addr) {
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switch (addr) {
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case SM501_SYSTEM_CONTROL:
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s->system_control = value & 0xE300B8F7;
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break;
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@ -805,7 +805,7 @@ static void sm501_system_config_write(void *opaque, hwaddr addr,
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break;
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case SM501_DRAM_CONTROL:
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s->local_mem_size_index = (value >> 13) & 0x7;
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/* rODO : check validity of size change */
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/* TODO : check validity of size change */
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s->dram_control |= value & 0x7FFFFFC3;
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break;
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case SM501_IRQ_MASK:
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@ -843,20 +843,20 @@ static const MemoryRegionOps sm501_system_config_ops = {
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|
||||
static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
|
||||
{
|
||||
SM501State * s = (SM501State *)opaque;
|
||||
SM501State *s = (SM501State *)opaque;
|
||||
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
|
||||
|
||||
/* TODO : consider BYTE/WORD access */
|
||||
/* TODO : consider endian */
|
||||
|
||||
assert(range_covers_byte(0, 0x400 * 3, addr));
|
||||
return *(uint32_t*)&s->dc_palette[addr];
|
||||
return *(uint32_t *)&s->dc_palette[addr];
|
||||
}
|
||||
|
||||
static void sm501_palette_write(void *opaque,
|
||||
hwaddr addr, uint32_t value)
|
||||
static void sm501_palette_write(void *opaque, hwaddr addr,
|
||||
uint32_t value)
|
||||
{
|
||||
SM501State * s = (SM501State *)opaque;
|
||||
SM501State *s = (SM501State *)opaque;
|
||||
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
|
||||
(int)addr, value);
|
||||
|
||||
|
|
@ -864,17 +864,17 @@ static void sm501_palette_write(void *opaque,
|
|||
/* TODO : consider endian */
|
||||
|
||||
assert(range_covers_byte(0, 0x400 * 3, addr));
|
||||
*(uint32_t*)&s->dc_palette[addr] = value;
|
||||
*(uint32_t *)&s->dc_palette[addr] = value;
|
||||
}
|
||||
|
||||
static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
|
||||
unsigned size)
|
||||
{
|
||||
SM501State * s = (SM501State *)opaque;
|
||||
SM501State *s = (SM501State *)opaque;
|
||||
uint32_t ret = 0;
|
||||
SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
|
||||
|
||||
switch(addr) {
|
||||
switch (addr) {
|
||||
|
||||
case SM501_DC_PANEL_CONTROL:
|
||||
ret = s->dc_panel_control;
|
||||
|
|
@ -949,7 +949,7 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
|
|||
ret = s->dc_crt_hwc_color_3;
|
||||
break;
|
||||
|
||||
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
|
||||
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
|
||||
ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
|
||||
break;
|
||||
|
||||
|
|
@ -965,11 +965,11 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
|
|||
static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
|
||||
uint64_t value, unsigned size)
|
||||
{
|
||||
SM501State * s = (SM501State *)opaque;
|
||||
SM501State *s = (SM501State *)opaque;
|
||||
SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
|
||||
(unsigned)addr, (unsigned)value);
|
||||
|
||||
switch(addr) {
|
||||
switch (addr) {
|
||||
case SM501_DC_PANEL_CONTROL:
|
||||
s->dc_panel_control = value & 0x0FFF73FF;
|
||||
break;
|
||||
|
|
@ -1056,7 +1056,7 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
|
|||
s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
|
||||
break;
|
||||
|
||||
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
|
||||
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
|
||||
sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
|
||||
break;
|
||||
|
||||
|
|
@ -1080,11 +1080,11 @@ static const MemoryRegionOps sm501_disp_ctrl_ops = {
|
|||
static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
|
||||
unsigned size)
|
||||
{
|
||||
SM501State * s = (SM501State *)opaque;
|
||||
SM501State *s = (SM501State *)opaque;
|
||||
uint32_t ret = 0;
|
||||
SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr);
|
||||
|
||||
switch(addr) {
|
||||
switch (addr) {
|
||||
case SM501_2D_SOURCE_BASE:
|
||||
ret = s->twoD_source_base;
|
||||
break;
|
||||
|
|
@ -1100,11 +1100,11 @@ static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
|
|||
static void sm501_2d_engine_write(void *opaque, hwaddr addr,
|
||||
uint64_t value, unsigned size)
|
||||
{
|
||||
SM501State * s = (SM501State *)opaque;
|
||||
SM501State *s = (SM501State *)opaque;
|
||||
SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
|
||||
(unsigned)addr, (unsigned)value);
|
||||
|
||||
switch(addr) {
|
||||
switch (addr) {
|
||||
case SM501_2D_SOURCE:
|
||||
s->twoD_source = value;
|
||||
break;
|
||||
|
|
@ -1170,7 +1170,7 @@ static const MemoryRegionOps sm501_2d_engine_ops = {
|
|||
typedef void draw_line_func(uint8_t *d, const uint8_t *s,
|
||||
int width, const uint32_t *pal);
|
||||
|
||||
typedef void draw_hwc_line_func(SM501State * s, int crt, uint8_t * palette,
|
||||
typedef void draw_hwc_line_func(SM501State *s, int crt, uint8_t *palette,
|
||||
int c_y, uint8_t *d, int width);
|
||||
|
||||
#define DEPTH 8
|
||||
|
|
@ -1197,7 +1197,7 @@ typedef void draw_hwc_line_func(SM501State * s, int crt, uint8_t * palette,
|
|||
#define DEPTH 32
|
||||
#include "sm501_template.h"
|
||||
|
||||
static draw_line_func * draw_line8_funcs[] = {
|
||||
static draw_line_func *draw_line8_funcs[] = {
|
||||
draw_line8_8,
|
||||
draw_line8_15,
|
||||
draw_line8_16,
|
||||
|
|
@ -1207,7 +1207,7 @@ static draw_line_func * draw_line8_funcs[] = {
|
|||
draw_line8_16bgr,
|
||||
};
|
||||
|
||||
static draw_line_func * draw_line16_funcs[] = {
|
||||
static draw_line_func *draw_line16_funcs[] = {
|
||||
draw_line16_8,
|
||||
draw_line16_15,
|
||||
draw_line16_16,
|
||||
|
|
@ -1217,7 +1217,7 @@ static draw_line_func * draw_line16_funcs[] = {
|
|||
draw_line16_16bgr,
|
||||
};
|
||||
|
||||
static draw_line_func * draw_line32_funcs[] = {
|
||||
static draw_line_func *draw_line32_funcs[] = {
|
||||
draw_line32_8,
|
||||
draw_line32_15,
|
||||
draw_line32_16,
|
||||
|
|
@ -1227,7 +1227,7 @@ static draw_line_func * draw_line32_funcs[] = {
|
|||
draw_line32_16bgr,
|
||||
};
|
||||
|
||||
static draw_hwc_line_func * draw_hwc_line_funcs[] = {
|
||||
static draw_hwc_line_func *draw_hwc_line_funcs[] = {
|
||||
draw_hwc_line_8,
|
||||
draw_hwc_line_15,
|
||||
draw_hwc_line_16,
|
||||
|
|
@ -1256,22 +1256,22 @@ static inline int get_depth_index(DisplaySurface *surface)
|
|||
}
|
||||
}
|
||||
|
||||
static void sm501_draw_crt(SM501State * s)
|
||||
static void sm501_draw_crt(SM501State *s)
|
||||
{
|
||||
DisplaySurface *surface = qemu_console_surface(s->con);
|
||||
int y;
|
||||
int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
|
||||
int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
|
||||
|
||||
uint8_t * src = s->local_mem;
|
||||
uint8_t *src = s->local_mem;
|
||||
int src_bpp = 0;
|
||||
int dst_bpp = surface_bytes_per_pixel(surface);
|
||||
uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
|
||||
- SM501_DC_PANEL_PALETTE];
|
||||
uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE -
|
||||
SM501_DC_PANEL_PALETTE];
|
||||
uint8_t hwc_palette[3 * 3];
|
||||
int ds_depth_index = get_depth_index(surface);
|
||||
draw_line_func * draw_line = NULL;
|
||||
draw_hwc_line_func * draw_hwc_line = NULL;
|
||||
draw_line_func *draw_line = NULL;
|
||||
draw_hwc_line_func *draw_hwc_line = NULL;
|
||||
int full_update = 0;
|
||||
int y_start = -1;
|
||||
ram_addr_t page_min = ~0l;
|
||||
|
|
@ -1344,17 +1344,20 @@ static void sm501_draw_crt(SM501State * s)
|
|||
/* draw graphics layer */
|
||||
draw_line(d, src, width, palette);
|
||||
|
||||
/* draw haredware cursor */
|
||||
/* draw hardware cursor */
|
||||
if (update_hwc) {
|
||||
draw_hwc_line(s, 1, hwc_palette, y - get_hwc_y(s, 1), d, width);
|
||||
}
|
||||
|
||||
if (y_start < 0)
|
||||
if (y_start < 0) {
|
||||
y_start = y;
|
||||
if (page0 < page_min)
|
||||
}
|
||||
if (page0 < page_min) {
|
||||
page_min = page0;
|
||||
if (page1 > page_max)
|
||||
}
|
||||
if (page1 > page_max) {
|
||||
page_max = page1;
|
||||
}
|
||||
} else {
|
||||
if (y_start >= 0) {
|
||||
/* flush to display */
|
||||
|
|
@ -1368,8 +1371,9 @@ static void sm501_draw_crt(SM501State * s)
|
|||
}
|
||||
|
||||
/* complete flush to display */
|
||||
if (y_start >= 0)
|
||||
if (y_start >= 0) {
|
||||
dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
|
||||
}
|
||||
|
||||
/* clear dirty flags */
|
||||
if (page_min != ~0l) {
|
||||
|
|
@ -1381,10 +1385,11 @@ static void sm501_draw_crt(SM501State * s)
|
|||
|
||||
static void sm501_update_display(void *opaque)
|
||||
{
|
||||
SM501State * s = (SM501State *)opaque;
|
||||
SM501State *s = (SM501State *)opaque;
|
||||
|
||||
if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
|
||||
if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) {
|
||||
sm501_draw_crt(s);
|
||||
}
|
||||
}
|
||||
|
||||
static const GraphicHwOps sm501_ops = {
|
||||
|
|
@ -1394,17 +1399,16 @@ static const GraphicHwOps sm501_ops = {
|
|||
void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
|
||||
uint32_t local_mem_bytes, qemu_irq irq, Chardev *chr)
|
||||
{
|
||||
SM501State * s;
|
||||
SM501State *s;
|
||||
DeviceState *dev;
|
||||
MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1);
|
||||
|
||||
/* allocate management data region */
|
||||
s = (SM501State *)g_malloc0(sizeof(SM501State));
|
||||
s = g_new0(SM501State, 1);
|
||||
s->base = base;
|
||||
s->local_mem_size_index
|
||||
= get_local_mem_size_index(local_mem_bytes);
|
||||
s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
|
||||
SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
|
||||
s->local_mem_size_index);
|
||||
s->system_control = 0x00100000;
|
||||
|
|
@ -1421,8 +1425,8 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
|
|||
memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
|
||||
|
||||
/* map mmio */
|
||||
memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops, s,
|
||||
"sm501-system-config", 0x6c);
|
||||
memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops,
|
||||
s, "sm501-system-config", 0x6c);
|
||||
memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
|
||||
sm501_system_config);
|
||||
memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s,
|
||||
|
|
|
|||
|
|
@ -51,10 +51,10 @@ static void glue(draw_line8_, PIXEL_NAME)(
|
|||
r = (pal[v] >> 16) & 0xff;
|
||||
g = (pal[v] >> 8) & 0xff;
|
||||
b = (pal[v] >> 0) & 0xff;
|
||||
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
s ++;
|
||||
*(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
s++;
|
||||
d += BPP;
|
||||
} while (-- width != 0);
|
||||
} while (--width != 0);
|
||||
}
|
||||
|
||||
static void glue(draw_line16_, PIXEL_NAME)(
|
||||
|
|
@ -68,10 +68,10 @@ static void glue(draw_line16_, PIXEL_NAME)(
|
|||
r = ((rgb565 >> 11) & 0x1f) << 3;
|
||||
g = ((rgb565 >> 5) & 0x3f) << 2;
|
||||
b = ((rgb565 >> 0) & 0x1f) << 3;
|
||||
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
*(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
s += 2;
|
||||
d += BPP;
|
||||
} while (-- width != 0);
|
||||
} while (--width != 0);
|
||||
}
|
||||
|
||||
static void glue(draw_line32_, PIXEL_NAME)(
|
||||
|
|
@ -90,17 +90,17 @@ static void glue(draw_line32_, PIXEL_NAME)(
|
|||
g = s[1];
|
||||
r = s[2];
|
||||
#endif
|
||||
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
*(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
s += 4;
|
||||
d += BPP;
|
||||
} while (-- width != 0);
|
||||
} while (--width != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Draw hardware cursor image on the given line.
|
||||
*/
|
||||
static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State * s, int crt,
|
||||
uint8_t * palette, int c_y, uint8_t *d, int width)
|
||||
static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *s, int crt,
|
||||
uint8_t *palette, int c_y, uint8_t *d, int width)
|
||||
{
|
||||
int x, i;
|
||||
uint8_t bitset = 0;
|
||||
|
|
@ -132,7 +132,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State * s, int crt,
|
|||
uint8_t r = palette[v * 3 + 0];
|
||||
uint8_t g = palette[v * 3 + 1];
|
||||
uint8_t b = palette[v * 3 + 2];
|
||||
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
*(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
|
||||
}
|
||||
d += BPP;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue