mirror of https://github.com/xqemu/xqemu.git
target-i386: Introduce mo_stacksize
Centralize computation of a MO_SIZE for the stack pointer. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-3-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -304,6 +304,12 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
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}
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}
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}
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}
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/* Select the size of the stack pointer. */
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static inline TCGMemOp mo_stacksize(DisasContext *s)
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{
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return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;
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}
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/* Select only size 64 else 32. Used for SSE operand sizes. */
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/* Select only size 64 else 32. Used for SSE operand sizes. */
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static inline TCGMemOp mo_64_32(TCGMemOp ot)
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static inline TCGMemOp mo_64_32(TCGMemOp ot)
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{
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{
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@ -2289,31 +2295,22 @@ gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
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static inline void gen_stack_update(DisasContext *s, int addend)
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static inline void gen_stack_update(DisasContext *s, int addend)
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{
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{
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#ifdef TARGET_X86_64
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gen_op_add_reg_im(mo_stacksize(s), R_ESP, addend);
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if (CODE64(s)) {
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gen_op_add_reg_im(MO_64, R_ESP, addend);
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} else
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#endif
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if (s->ss32) {
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gen_op_add_reg_im(MO_32, R_ESP, addend);
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} else {
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gen_op_add_reg_im(MO_16, R_ESP, addend);
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}
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}
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}
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/* Generate a push. It depends on ss32, addseg and dflag. */
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/* Generate a push. It depends on ss32, addseg and dflag. */
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static void gen_push_v(DisasContext *s, TCGv val)
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static void gen_push_v(DisasContext *s, TCGv val)
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{
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{
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TCGMemOp a_ot, d_ot = mo_pushpop(s, s->dflag);
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TCGMemOp d_ot = mo_pushpop(s, s->dflag);
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TCGMemOp a_ot = mo_stacksize(s);
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int size = 1 << d_ot;
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int size = 1 << d_ot;
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TCGv new_esp = cpu_A0;
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TCGv new_esp = cpu_A0;
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tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size);
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tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size);
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if (CODE64(s)) {
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if (CODE64(s)) {
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a_ot = MO_64;
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/* No special handling. */
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} else if (s->ss32) {
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} else if (s->ss32) {
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a_ot = MO_32;
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if (s->addseg) {
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if (s->addseg) {
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new_esp = cpu_tmp4;
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new_esp = cpu_tmp4;
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tcg_gen_mov_tl(new_esp, cpu_A0);
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tcg_gen_mov_tl(new_esp, cpu_A0);
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@ -2322,7 +2319,6 @@ static void gen_push_v(DisasContext *s, TCGv val)
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tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
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tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
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}
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}
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} else {
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} else {
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a_ot = MO_16;
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new_esp = cpu_tmp4;
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new_esp = cpu_tmp4;
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tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
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tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
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tcg_gen_mov_tl(new_esp, cpu_A0);
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tcg_gen_mov_tl(new_esp, cpu_A0);
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