ShuriZma
/
xqemu
mirror of https://github.com/xqemu/xqemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target-arm: Translate with VFP-enabled from TB flags, not CPUState 

When translating code, whether the VFP unit is enabled for this TB
is stored in a bit in the TB flags. Use this rather than incorrectly
reading the FPEXC from the CPUState passed to translation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-01-14 20:39:19 +01:00 committed by Aurelien Jarno
parent a170576856
commit 5df8bac1d3
1 changed files with 5 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
target-arm/translate.c
View File

@ -59,6 +59,7 @@ typedef struct DisasContext {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
int user; int user;
#endif #endif
int vfp_enabled;
} DisasContext; } DisasContext;
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
@ -2603,12 +2604,6 @@ static void gen_vfp_msr(TCGv tmp)
dead_tmp(tmp); dead_tmp(tmp);
} }
static inline int
vfp_enabled(CPUState * env)
{
return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0);
}
static void gen_neon_dup_u8(TCGv var, int shift) static void gen_neon_dup_u8(TCGv var, int shift)
{ {
TCGv tmp = new_tmp(); TCGv tmp = new_tmp();
@ -2653,7 +2648,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
if (!arm_feature(env, ARM_FEATURE_VFP)) if (!arm_feature(env, ARM_FEATURE_VFP))
return 1; return 1;
if (!vfp_enabled(env)) { if (!s->vfp_enabled) {
/* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */ /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
if ((insn & 0x0fe00fff) != 0x0ee00a10) if ((insn & 0x0fe00fff) != 0x0ee00a10)
return 1; return 1;
@ -3804,7 +3799,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
TCGv tmp2; TCGv tmp2;
TCGv_i64 tmp64; TCGv_i64 tmp64;
if (!vfp_enabled(env)) if (!s->vfp_enabled)
return 1; return 1;
VFP_DREG_D(rd, insn); VFP_DREG_D(rd, insn);
rn = (insn >> 16) & 0xf; rn = (insn >> 16) & 0xf;
@ -4199,7 +4194,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
TCGv tmp, tmp2, tmp3, tmp4, tmp5; TCGv tmp, tmp2, tmp3, tmp4, tmp5;
TCGv_i64 tmp64; TCGv_i64 tmp64;
if (!vfp_enabled(env)) if (!s->vfp_enabled)
return 1; return 1;
q = (insn & (1 << 6)) != 0; q = (insn & (1 << 6)) != 0;
u = (insn >> 24) & 1; u = (insn >> 24) & 1;
@ -9108,6 +9103,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR; dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
} }
#endif #endif
dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
cpu_F0s = tcg_temp_new_i32(); cpu_F0s = tcg_temp_new_i32();
cpu_F1s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32();
cpu_F0d = tcg_temp_new_i64(); cpu_F0d = tcg_temp_new_i64();