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target-arm: A64: Implement AES instructions 

Implement the AES instructions from the optional Crypto Extensions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401458125-27977-8-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2014-06-09 15:43:25 +01:00
parent aa633469ed
commit 5acc765c04
2 changed files with 51 additions and 1 deletions
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1
linux-user/elfload.c
View File

@ -539,6 +539,7 @@ static uint32_t get_elf_hwcap(void)
/* probe for the extra features */ /* probe for the extra features */
#define GET_FEATURE(feat, hwcap) \ #define GET_FEATURE(feat, hwcap) \
do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0) do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_AES);
GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL); GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL);
GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32);
#undef GET_FEATURE #undef GET_FEATURE

51
target-arm/translate-a64.c
View File

@ -85,6 +85,7 @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
/* initialize TCG globals. */ /* initialize TCG globals. */
void a64_translate_init(void) void a64_translate_init(void)
@ -10549,7 +10550,55 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
*/ */
static void disas_crypto_aes(DisasContext *s, uint32_t insn) static void disas_crypto_aes(DisasContext *s, uint32_t insn)
{ {
unsupported_encoding(s, insn); int size = extract32(insn, 22, 2);
int opcode = extract32(insn, 12, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
int decrypt;
TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_decrypt;
CryptoThreeOpEnvFn *genfn;
if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
|| size != 0) {
unallocated_encoding(s);
return;
}
switch (opcode) {
case 0x4: /* AESE */
decrypt = 0;
genfn = gen_helper_crypto_aese;
break;
case 0x6: /* AESMC */
decrypt = 0;
genfn = gen_helper_crypto_aesmc;
break;
case 0x5: /* AESD */
decrypt = 1;
genfn = gen_helper_crypto_aese;
break;
case 0x7: /* AESIMC */
decrypt = 1;
genfn = gen_helper_crypto_aesmc;
break;
default:
unallocated_encoding(s);
return;
}
/* Note that we convert the Vx register indexes into the
* index within the vfp.regs[] array, so we can share the
* helper with the AArch32 instructions.
*/
tcg_rd_regno = tcg_const_i32(rd << 1);
tcg_rn_regno = tcg_const_i32(rn << 1);
tcg_decrypt = tcg_const_i32(decrypt);
genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_decrypt);
tcg_temp_free_i32(tcg_rd_regno);
tcg_temp_free_i32(tcg_rn_regno);
tcg_temp_free_i32(tcg_decrypt);
} }
/* C3.6.20 Crypto three-reg SHA /* C3.6.20 Crypto three-reg SHA