ShuriZma
/
xqemu
mirror of https://github.com/xqemu/xqemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

-----BEGIN PGP SIGNATURE----- 

Version: GnuPG v1
 
 iQEcBAABAgAGBQJXOxduAAoJEJykq7OBq3PIm5UIAJajKxxkr97i0JicU18FYU6Y
 LHTNRwfmVxJ3VY00v4J9oMFtu4jBVHn6wREtPCL8rEnXSzO0gfjJ9Hy49t/F9Apq
 e/ZMWzmmdNuJamf1/19KnlGhhWQb41jYW+W7i8j2jDRzmxmtZ5JajfAIokX1roVY
 22vHMpTjRKEEWv4TRyY+f199wtwzAXbTghLYj8/EJGtyIoWcT44fzqU3SBmg5ou7
 DP18SfEHoUCDA7ffMnP1gu7XZdZOUEcpXGhRrFEN//XPc7jWUqdUtjmFeX/VcpSZ
 I4Zq8HXnWz9fCf0MeDWpMKsRAGy38IHSg1avHtcRQdwRfxT0bW2CjKbnyheH75o=
 =a1OG
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging

# gpg: Signature made Tue 17 May 2016 14:06:54 BST using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>"

* remotes/stefanha/tags/tracing-pull-request:
  hw/intc/arm_gic: add tracepoints

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2016-05-17 14:07:25 +01:00
parent 3f5e34a45c 2531088f6c
commit 5a3fd960f3
2 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
hw/intc/arm_gic.c
View File

@ -23,6 +23,7 @@
#include "gic_internal.h"
#include "qapi/error.h"
#include "qom/cpu.h"
#include "trace.h"
//#define DEBUG_GIC
@ -93,6 +94,11 @@ void gic_update(GICState *s)
}
}
if (best_irq != 1023) {
trace_gic_update_bestirq(cpu, best_irq, best_prio,
s->priority_mask[cpu], s->running_priority[cpu]);
}
irq_level = fiq_level = 0;
if (best_prio < s->priority_mask[cpu]) {
@ -106,10 +112,12 @@ void gic_update(GICState *s)
DPRINTF("Raised pending FIQ %d (cpu %d)\n",
best_irq, cpu);
fiq_level = 1;
trace_gic_update_set_irq(cpu, "fiq", fiq_level);
} else {
DPRINTF("Raised pending IRQ %d (cpu %d)\n",
best_irq, cpu);
irq_level = 1;
trace_gic_update_set_irq(cpu, "irq", irq_level);
}
}
}
@ -197,6 +205,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
} else {
gic_set_irq_generic(s, irq, level, cm, target);
}
trace_gic_set_irq(irq, level, cm, target);
gic_update(s);
}
@ -332,6 +341,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
* is in the wrong group.
*/
irq = gic_get_current_pending_irq(s, cpu, attrs);
trace_gic_acknowledge_irq(cpu, irq);
if (irq >= GIC_MAXIRQ) {
DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq);
@ -853,6 +863,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
if (!GIC_TEST_ENABLED(irq + i, cm)) {
DPRINTF("Enabled IRQ %d\n", irq + i);
trace_gic_enable_irq(irq + i);
}
GIC_SET_ENABLED(irq + i, cm);
/* If a raised level triggered IRQ enabled then mark
@ -879,6 +890,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
if (GIC_TEST_ENABLED(irq + i, cm)) {
DPRINTF("Disabled IRQ %d\n", irq + i);
trace_gic_disable_irq(irq + i);
}
GIC_CLEAR_ENABLED(irq + i, cm);
}

8
trace-events
View File

@ -1908,3 +1908,11 @@ aspeed_vic_update_fiq(int flags) "Raising FIQ: %d"
aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
# hw/intc/arm_gic.c
gic_enable_irq(int irq) "irq %d enabled"
gic_disable_irq(int irq) "irq %d disabled"
gic_set_irq(int irq, int level, int cpumask, int target) "irq %d level %d cpumask 0x%x target 0x%x"
gic_update_bestirq(int cpu, int irq, int prio, int priority_mask, int running_priority) "cpu %d irq %d priority %d cpu priority mask %d cpu running priority %d"
gic_update_set_irq(int cpu, const char *name, int level) "cpu[%d]: %s = %d"
gic_acknowledge_irq(int cpu, int irq) "cpu %d acknowledged irq %d"