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Convert andn, orn and xnor to TCG 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4030 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-03-09 20:46:51 +00:00
parent 3f47aa8c37
commit 56ec06bb8e
2 changed files with 6 additions and 18 deletions
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15
target-sparc/op.c
View File

@ -554,21 +554,6 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
FORCE_RET(); FORCE_RET();
} }
void OPPROTO op_andn_T1_T0(void)
{
T0 &= ~T1;
}
void OPPROTO op_orn_T1_T0(void)
{
T0 |= ~T1;
}
void OPPROTO op_xnor_T1_T0(void)
{
T0 ^= ~T1;
}
void OPPROTO op_umul_T1_T0(void) void OPPROTO op_umul_T1_T0(void)
{ {
uint64_t res; uint64_t res;

9
target-sparc/translate.c
View File

@ -2613,17 +2613,20 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
break; break;
case 0x5: case 0x5:
gen_op_andn_T1_T0(); tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
if (xop & 0x10) if (xop & 0x10)
gen_op_logic_T0_cc(); gen_op_logic_T0_cc();
break; break;
case 0x6: case 0x6:
gen_op_orn_T1_T0(); tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
if (xop & 0x10) if (xop & 0x10)
gen_op_logic_T0_cc(); gen_op_logic_T0_cc();
break; break;
case 0x7: case 0x7:
gen_op_xnor_T1_T0(); tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
if (xop & 0x10) if (xop & 0x10)
gen_op_logic_T0_cc(); gen_op_logic_T0_cc();
break; break;