mirror of https://github.com/xqemu/xqemu.git
ppc patch queue for 2017-03-06
Looks like my previous batch wasn't quite the last before hard freeze. This has a handful of bugfixes to go in. They're all genuine bugfixes, though not regressions in some cases. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJYvOCUAAoJEGw4ysog2bOSQWgQAKzPeIqz8I/1eXL+zmZCUaiU J2gyjzfaKkQ/AVGPtT45ZjJsihxSFbZT6koxXtEaxwq5DD87yXQOqA/d+BH7jr5d 75FGjVzKOA0IKQymySztwoC2j/ftWmmSx0N6YUmL0QcXCISS1YHRvdQkdXf6j4I/ XtK1FA34wmCsTK1AgZ9WDxjABdkHP+7FDRBpVmr01Nv1TeK2Xms2MqJ5Wku/lOX/ 6bg1KbC8pVHy5YZhIpRFzgGxaMr2UcJ0Q3YR9fD/4UW/k518sJk+i2xlagVsFxyG gqfPolv0wjwuGpYt42UyFG4IouCbKN+MChU5MBIaqU10VouOw+0/W+p+1ZOHgdB8 GoaBGyfuJ6/i4EQL0/+FL4hPOI5vHLliWxPfMJxDL5ujP0cFaPm2XbK5Yqxksu3m uYp3yYIbiSaF8QUxbBjAAoKPdVpP5dsgHjAlxecwCUGlIo0Ur3uphnU5lPoNlvS4 5ZcDDlMGjPb0oIHfdPt2ai8g+32uAsD7X7pi+qI0x+srSnjisRpOT2wKv0otMbGx U4j01/Na2DjFjhGW+vNm9UYsE/QgKr6pU9z3jUXOIplX1HBXirtfv5C/OypCN7Zj LgqsmiMWMJFjSLk8N8cxeM1w839B3wEM+2+46su7/qpW9sd0jKvHk0cJDyZPzn29 zQ52CbQQiewXM8y+mffe =/RZL -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170306' into staging ppc patch queue for 2017-03-06 Looks like my previous batch wasn't quite the last before hard freeze. This has a handful of bugfixes to go in. They're all genuine bugfixes, though not regressions in some cases. # gpg: Signature made Mon 06 Mar 2017 04:07:48 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.9-20170306: target/ppc: use helper for excp handling target/ppc: fmadd: add macro for updating flags target/ppc: fmadd check for excp independently spapr: ensure that all threads within core are on the same NUMA node ppc/xics: register reset handlers for the ICP and ICS objects Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
56b51708e9
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@ -333,7 +333,7 @@ static const VMStateDescription vmstate_icp_server = {
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},
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};
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static void icp_reset(DeviceState *dev)
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static void icp_reset(void *dev)
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{
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ICPState *icp = ICP(dev);
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@ -359,6 +359,8 @@ static void icp_realize(DeviceState *dev, Error **errp)
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}
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icp->xics = XICS_FABRIC(obj);
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qemu_register_reset(icp_reset, dev);
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}
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@ -366,7 +368,6 @@ static void icp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = icp_reset;
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dc->vmsd = &vmstate_icp_server;
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dc->realize = icp_realize;
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}
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@ -522,7 +523,7 @@ static void ics_simple_eoi(ICSState *ics, uint32_t nr)
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}
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}
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static void ics_simple_reset(DeviceState *dev)
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static void ics_simple_reset(void *dev)
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{
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ICSState *ics = ICS_SIMPLE(dev);
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int i;
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@ -611,6 +612,8 @@ static void ics_simple_realize(DeviceState *dev, Error **errp)
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}
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ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
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ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
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qemu_register_reset(ics_simple_reset, dev);
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}
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static Property ics_simple_properties[] = {
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@ -626,7 +629,6 @@ static void ics_simple_class_init(ObjectClass *klass, void *data)
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isc->realize = ics_simple_realize;
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dc->props = ics_simple_properties;
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dc->vmsd = &vmstate_ics_simple;
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dc->reset = ics_simple_reset;
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isc->reject = ics_simple_reject;
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isc->resend = ics_simple_resend;
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isc->eoi = ics_simple_eoi;
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@ -102,7 +102,7 @@ static int icp_set_kvm_state(ICPState *icp, int version_id)
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return 0;
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}
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static void icp_kvm_reset(DeviceState *dev)
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static void icp_kvm_reset(void *dev)
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{
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ICPState *icp = ICP(dev);
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@ -146,12 +146,17 @@ static void icp_kvm_cpu_setup(ICPState *icp, PowerPCCPU *cpu)
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icp->cap_irq_xics_enabled = true;
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}
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static void icp_kvm_realize(DeviceState *dev, Error **errp)
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{
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qemu_register_reset(icp_kvm_reset, dev);
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}
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static void icp_kvm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ICPStateClass *icpc = ICP_CLASS(klass);
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dc->reset = icp_kvm_reset;
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dc->realize = icp_kvm_realize;
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icpc->pre_save = icp_get_kvm_state;
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icpc->post_load = icp_set_kvm_state;
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icpc->cpu_setup = icp_kvm_cpu_setup;
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@ -293,7 +298,7 @@ static void ics_kvm_set_irq(void *opaque, int srcno, int val)
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}
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}
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static void ics_kvm_reset(DeviceState *dev)
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static void ics_kvm_reset(void *dev)
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{
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ICSState *ics = ICS_SIMPLE(dev);
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int i;
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@ -324,15 +329,15 @@ static void ics_kvm_realize(DeviceState *dev, Error **errp)
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}
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ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
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ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs);
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qemu_register_reset(ics_kvm_reset, dev);
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}
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static void ics_kvm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ICSStateClass *icsc = ICS_BASE_CLASS(klass);
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icsc->realize = ics_kvm_realize;
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dc->reset = ics_kvm_reset;
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icsc->pre_save = ics_get_kvm_state;
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icsc->post_load = ics_set_kvm_state;
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}
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@ -106,7 +106,6 @@ static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics,
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int i;
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ics = ICS_SIMPLE(object_new(type_ics));
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qdev_set_parent_bus(DEVICE(ics), sysbus_get_default());
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object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL);
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object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err);
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object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL);
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@ -123,7 +122,6 @@ static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics,
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ICPState *icp = &spapr->icps[i];
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object_initialize(icp, sizeof(*icp), type_icp);
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qdev_set_parent_bus(DEVICE(icp), sysbus_get_default());
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object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL);
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object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL);
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object_property_set_bool(OBJECT(icp), true, "realized", &err);
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@ -63,8 +63,6 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
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Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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int i;
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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@ -82,12 +80,6 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
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}
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}
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/* Set NUMA node for the added CPUs */
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i = numa_get_node_for_cpu(cs->cpu_index);
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if (i < nb_numa_nodes) {
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cs->numa_node = i;
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}
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xics_cpu_setup(XICS_FABRIC(spapr), cpu);
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qemu_register_reset(spapr_cpu_reset, cpu);
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@ -171,11 +163,13 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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const char *typename = object_class_get_name(scc->cpu_class);
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size_t size = object_type_get_instance_size(typename);
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Error *local_err = NULL;
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int core_node_id = numa_get_node_for_cpu(cc->core_id);;
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void *obj;
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int i, j;
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sc->threads = g_malloc0(size * cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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int node_id;
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char id[32];
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CPUState *cs;
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@ -184,6 +178,19 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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object_initialize(obj, size, typename);
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cs = CPU(obj);
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cs->cpu_index = cc->core_id + i;
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/* Set NUMA node for the added CPUs */
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node_id = numa_get_node_for_cpu(cs->cpu_index);
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if (node_id != core_node_id) {
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error_setg(&local_err, "Invalid node-id=%d of thread[cpu-index: %d]"
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" on CPU[core-id: %d, node-id: %d], node-id must be the same",
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node_id, cs->cpu_index, cc->core_id, core_node_id);
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goto err;
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}
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if (node_id < nb_numa_nodes) {
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cs->numa_node = node_id;
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}
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snprintf(id, sizeof(id), "thread[%d]", i);
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object_property_add_child(OBJECT(sc), id, obj, &local_err);
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if (local_err) {
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@ -743,34 +743,38 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
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return do_fri(env, arg, float_round_down);
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}
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static void float64_maddsub_update_excp(CPUPPCState *env, float64 arg1,
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float64 arg2, float64 arg3,
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unsigned int madd_flags)
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{
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if (unlikely((float64_is_infinity(arg1) && float64_is_zero(arg2)) ||
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(float64_is_zero(arg1) && float64_is_infinity(arg2)))) {
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/* Multiplication of zero by infinity */
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arg1 = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
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} else if (unlikely(float64_is_signaling_nan(arg1, &env->fp_status) ||
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float64_is_signaling_nan(arg2, &env->fp_status) ||
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float64_is_signaling_nan(arg3, &env->fp_status))) {
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/* sNaN operation */
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
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} else if ((float64_is_infinity(arg1) || float64_is_infinity(arg2)) &&
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float64_is_infinity(arg3)) {
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uint8_t aSign, bSign, cSign;
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aSign = float64_is_neg(arg1);
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bSign = float64_is_neg(arg2);
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cSign = float64_is_neg(arg3);
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if (madd_flags & float_muladd_negate_c) {
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cSign ^= 1;
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}
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if (aSign ^ bSign ^ cSign) {
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
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}
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}
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#define FPU_MADDSUB_UPDATE(NAME, TP) \
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static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \
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unsigned int madd_flags) \
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{ \
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if (TP##_is_signaling_nan(arg1, &env->fp_status) || \
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TP##_is_signaling_nan(arg2, &env->fp_status) || \
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TP##_is_signaling_nan(arg3, &env->fp_status)) { \
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/* sNaN operation */ \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
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} \
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if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \
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(TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \
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/* Multiplication of zero by infinity */ \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); \
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} \
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if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \
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TP##_is_infinity(arg3)) { \
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uint8_t aSign, bSign, cSign; \
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\
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aSign = TP##_is_neg(arg1); \
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bSign = TP##_is_neg(arg2); \
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cSign = TP##_is_neg(arg3); \
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if (madd_flags & float_muladd_negate_c) { \
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cSign ^= 1; \
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} \
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if (aSign ^ bSign ^ cSign) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); \
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} \
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} \
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}
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FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32)
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FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64)
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#define FPU_FMADD(op, madd_flags) \
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uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
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@ -2236,24 +2240,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
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env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
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\
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if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
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if (tp##_is_signaling_nan(xa.fld, &tstat) || \
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tp##_is_signaling_nan(b->fld, &tstat) || \
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tp##_is_signaling_nan(c->fld, &tstat)) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
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tstat.float_exception_flags &= ~float_flag_invalid; \
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} \
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if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) || \
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(tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) { \
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xt_out.fld = float64_to_##tp(float_invalid_op_excp(env, \
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POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \
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tstat.float_exception_flags &= ~float_flag_invalid; \
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} \
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if ((tstat.float_exception_flags & float_flag_invalid) && \
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((tp##_is_infinity(xa.fld) || \
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tp##_is_infinity(b->fld)) && \
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tp##_is_infinity(c->fld))) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
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} \
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tp##_maddsub_update_excp(env, xa.fld, b->fld, c->fld, maddflgs); \
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} \
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\
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if (r2sp) { \
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