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ppc405: Pass in address_space_mem to ppc405{cr, ep}_init 

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Richard Henderson 2011-08-11 16:07:17 -07:00 committed by Avi Kivity
parent 39186d8ab8
commit 52ce55a102
3 changed files with 32 additions and 28 deletions
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6
hw/ppc405.h
View File

@ -59,12 +59,14 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
uint32_t flags); uint32_t flags);
CPUState *ppc405cr_init (MemoryRegion ram_memories[4], CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
target_phys_addr_t ram_bases[4], target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4], target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp, uint32_t sysclk, qemu_irq **picp,
int do_init); int do_init);
CPUState *ppc405ep_init (MemoryRegion ram_memories[2], CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2], target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2], target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp, uint32_t sysclk, qemu_irq **picp,

8
hw/ppc405_boards.c
View File

@ -207,8 +207,8 @@ static void ref405ep_init (ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__); printf("%s: register cpu\n", __func__);
#endif #endif
env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, env = ppc405ep_init(get_system_memory(), ram_memories, ram_bases, ram_sizes,
kernel_filename == NULL ? 0 : 1); 33333333, &pic, kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */ /* allocate SRAM */
sram_size = 512 * 1024; sram_size = 512 * 1024;
sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size); sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
@ -534,8 +534,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__); printf("%s: register cpu\n", __func__);
#endif #endif
ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, ppc405ep_init(get_system_memory(), ram_memories, ram_bases, ram_sizes,
kernel_filename == NULL ? 0 : 1); 33333333, &pic, kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */ /* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("%s: register BIOS\n", __func__); printf("%s: register BIOS\n", __func__);

14
hw/ppc405_uc.c
View File

@ -2107,7 +2107,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
qemu_register_reset(ppc405cr_cpc_reset, cpc); qemu_register_reset(ppc405cr_cpc_reset, cpc);
} }
CPUState *ppc405cr_init (MemoryRegion ram_memories[4], CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
target_phys_addr_t ram_bases[4], target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4], target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp, uint32_t sysclk, qemu_irq **picp,
@ -2149,12 +2150,12 @@ CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
ppc405_dma_init(env, dma_irqs); ppc405_dma_init(env, dma_irqs);
/* Serial ports */ /* Serial ports */
if (serial_hds[0] != NULL) { if (serial_hds[0] != NULL) {
serial_mm_init(get_system_memory(), 0xef600300, 0, pic[0], serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
PPC_SERIAL_MM_BAUDBASE, serial_hds[0], PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
DEVICE_BIG_ENDIAN); DEVICE_BIG_ENDIAN);
} }
if (serial_hds[1] != NULL) { if (serial_hds[1] != NULL) {
serial_mm_init(get_system_memory(), 0xef600400, 0, pic[1], serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
PPC_SERIAL_MM_BAUDBASE, serial_hds[1], PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
DEVICE_BIG_ENDIAN); DEVICE_BIG_ENDIAN);
} }
@ -2455,7 +2456,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
#endif #endif
} }
CPUState *ppc405ep_init (MemoryRegion ram_memories[2], CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2], target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2], target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp, uint32_t sysclk, qemu_irq **picp,
@ -2506,12 +2508,12 @@ CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
ppc405_gpio_init(0xef600700); ppc405_gpio_init(0xef600700);
/* Serial ports */ /* Serial ports */
if (serial_hds[0] != NULL) { if (serial_hds[0] != NULL) {
serial_mm_init(get_system_memory(), 0xef600300, 0, pic[0], serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
PPC_SERIAL_MM_BAUDBASE, serial_hds[0], PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
DEVICE_BIG_ENDIAN); DEVICE_BIG_ENDIAN);
} }
if (serial_hds[1] != NULL) { if (serial_hds[1] != NULL) {
serial_mm_init(get_system_memory(), 0xef600400, 0, pic[1], serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
PPC_SERIAL_MM_BAUDBASE, serial_hds[1], PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
DEVICE_BIG_ENDIAN); DEVICE_BIG_ENDIAN);
} }