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hw/nand: Pass block device state to init function 

Pass the BlockDeviceState to the nand_init() function rather
than having it look it up via drive_get() itself.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
This commit is contained in:
Peter Maydell 2011-07-29 16:35:19 +01:00 committed by Andrzej Zaborowski
parent c4f05c8cf7
commit 522f253ca8
5 changed files with 15 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hw/axis_dev88.c
View File

@ -30,6 +30,7 @@
#include "loader.h" #include "loader.h"
#include "elf.h" #include "elf.h"
#include "cris-boot.h" #include "cris-boot.h"
#include "blockdev.h"
#define D(x) #define D(x)
#define DNAND(x) #define DNAND(x)
@ -251,6 +252,7 @@ void axisdev88_init (ram_addr_t ram_size,
CPUState *env; CPUState *env;
DeviceState *dev; DeviceState *dev;
SysBusDevice *s; SysBusDevice *s;
DriveInfo *nand;
qemu_irq irq[30], nmi[2], *cpu_irq; qemu_irq irq[30], nmi[2], *cpu_irq;
void *etraxfs_dmac; void *etraxfs_dmac;
struct etraxfs_dma_client *eth[2] = {NULL, NULL}; struct etraxfs_dma_client *eth[2] = {NULL, NULL};
@ -278,7 +280,9 @@ void axisdev88_init (ram_addr_t ram_size,
/* Attach a NAND flash to CS1. */ /* Attach a NAND flash to CS1. */
nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39); nand = drive_get(IF_MTD, 0, 0);
nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
NAND_MFR_STMICRO, 0x39);
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state, nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
DEVICE_NATIVE_ENDIAN); DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);

2
hw/flash.h
View File

@ -19,7 +19,7 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
/* nand.c */ /* nand.c */
typedef struct NANDFlashState NANDFlashState; typedef struct NANDFlashState NANDFlashState;
NANDFlashState *nand_init(int manf_id, int chip_id); NANDFlashState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);
void nand_done(NANDFlashState *s); void nand_done(NANDFlashState *s);
void nand_setpins(NANDFlashState *s, uint8_t cle, uint8_t ale, void nand_setpins(NANDFlashState *s, uint8_t cle, uint8_t ale,
uint8_t ce, uint8_t wp, uint8_t gnd); uint8_t ce, uint8_t wp, uint8_t gnd);

8
hw/nand.c
View File

@ -14,7 +14,6 @@
# include "hw.h" # include "hw.h"
# include "flash.h" # include "flash.h"
# include "blockdev.h" # include "blockdev.h"
/* FIXME: Pass block device as an argument. */
# define NAND_CMD_READ0 0x00 # define NAND_CMD_READ0 0x00
# define NAND_CMD_READ1 0x01 # define NAND_CMD_READ1 0x01
@ -451,20 +450,17 @@ uint8_t nand_getio(NANDFlashState *s)
return *(s->ioaddr ++); return *(s->ioaddr ++);
} }
NANDFlashState *nand_init(int manf_id, int chip_id) NANDFlashState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id)
{ {
int pagesize; int pagesize;
NANDFlashState *s; NANDFlashState *s;
DriveInfo *dinfo;
if (nand_flash_ids[chip_id].size == 0) { if (nand_flash_ids[chip_id].size == 0) {
hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__); hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
} }
s = (NANDFlashState *) qemu_mallocz(sizeof(NANDFlashState)); s = (NANDFlashState *) qemu_mallocz(sizeof(NANDFlashState));
dinfo = drive_get(IF_MTD, 0, 0); s->bdrv = bdrv;
if (dinfo)
s->bdrv = dinfo->bdrv;
s->manf_id = manf_id; s->manf_id = manf_id;
s->chip_id = chip_id; s->chip_id = chip_id;
s->size = nand_flash_ids[s->chip_id].size << 20; s->size = nand_flash_ids[s->chip_id].size << 20;

4
hw/spitz.c
View File

@ -169,11 +169,13 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
static int sl_nand_init(SysBusDevice *dev) { static int sl_nand_init(SysBusDevice *dev) {
int iomemtype; int iomemtype;
SLNANDState *s; SLNANDState *s;
DriveInfo *nand;
s = FROM_SYSBUS(SLNANDState, dev); s = FROM_SYSBUS(SLNANDState, dev);
s->ctl = 0; s->ctl = 0;
s->nand = nand_init(s->manf_id, s->chip_id); nand = drive_get(IF_MTD, 0, 0);
s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
iomemtype = cpu_register_io_memory(sl_readfn, iomemtype = cpu_register_io_memory(sl_readfn,
sl_writefn, s, DEVICE_NATIVE_ENDIAN); sl_writefn, s, DEVICE_NATIVE_ENDIAN);

5
hw/tc6393xb.c
View File

@ -12,6 +12,7 @@
#include "flash.h" #include "flash.h"
#include "console.h" #include "console.h"
#include "pixel_ops.h" #include "pixel_ops.h"
#include "blockdev.h"
#define IRQ_TC6393_NAND 0 #define IRQ_TC6393_NAND 0
#define IRQ_TC6393_MMC 1 #define IRQ_TC6393_MMC 1
@ -566,6 +567,7 @@ TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
{ {
int iomemtype; int iomemtype;
TC6393xbState *s; TC6393xbState *s;
DriveInfo *nand;
CPUReadMemoryFunc * const tc6393xb_readfn[] = { CPUReadMemoryFunc * const tc6393xb_readfn[] = {
tc6393xb_readb, tc6393xb_readb,
tc6393xb_readw, tc6393xb_readw,
@ -586,7 +588,8 @@ TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76); nand = drive_get(IF_MTD, 0, 0);
s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);
iomemtype = cpu_register_io_memory(tc6393xb_readfn, iomemtype = cpu_register_io_memory(tc6393xb_readfn,
tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN); tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN);