mirror of https://github.com/xqemu/xqemu.git
target/arm: Implement DBGVCR32_EL2 system register
The DBGVCR_EL2 system register is needed to run a 32-bit EL1 guest under a Linux EL2 64-bit hypervisor. Its only purpose is to provide AArch64 with access to the state of the DBGVCR AArch32 register. Since we only have a dummy DBGVCR, implement a corresponding dummy DBGVCR32_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -4066,6 +4066,13 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
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.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
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.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tda,
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.access = PL1_RW, .accessfn = access_tda,
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.type = ARM_CP_NOP },
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.type = ARM_CP_NOP },
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/* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
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* to save and restore a 32-bit guest's DBGVCR)
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*/
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{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
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.access = PL2_RW, .accessfn = access_tda,
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.type = ARM_CP_NOP },
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/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
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/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
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* Channel but Linux may try to access this register. The 32-bit
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* Channel but Linux may try to access this register. The 32-bit
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* alias is DBGDCCINT.
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* alias is DBGDCCINT.
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