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Remember the state of level-triggered interrupts 

(Hollis Blanchard)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4330 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-05-04 13:15:24 +00:00
parent 50bf72b384
commit 4c54e87568
1 changed files with 7 additions and 2 deletions
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9
hw/ppc4xx_devs.c
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@ -278,6 +278,7 @@ typedef struct ppcuic_t ppcuic_t;
struct ppcuic_t { struct ppcuic_t {
uint32_t dcr_base; uint32_t dcr_base;
int use_vectors; int use_vectors;
uint32_t level; /* Remembers the state of level-triggered interrupts. */
uint32_t uicsr; /* Status register */ uint32_t uicsr; /* Status register */
uint32_t uicer; /* Enable register */ uint32_t uicer; /* Enable register */
uint32_t uiccr; /* Critical register */ uint32_t uiccr; /* Critical register */
@ -385,10 +386,13 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
uic->uicsr |= mask; uic->uicsr |= mask;
} else { } else {
/* Level sensitive interrupt */ /* Level sensitive interrupt */
if (level == 1) if (level == 1) {
uic->uicsr |= mask; uic->uicsr |= mask;
else uic->level |= mask;
} else {
uic->uicsr &= ~mask; uic->uicsr &= ~mask;
uic->level &= ~mask;
}
} }
#ifdef DEBUG_UIC #ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) { if (loglevel & CPU_LOG_INT) {
@ -460,6 +464,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
switch (dcrn) { switch (dcrn) {
case DCR_UICSR: case DCR_UICSR:
uic->uicsr &= ~val; uic->uicsr &= ~val;
uic->uicsr |= uic->level;
ppcuic_trigger_irq(uic); ppcuic_trigger_irq(uic);
break; break;
case DCR_UICSRS: case DCR_UICSRS: