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target-ppc: Store Quadword Conditional Drops Size Bit 

The size and register information are encoded into the reserve_info field
of CPU state in the store conditional translation code.  Specifically, the
size is shifted left by 5 bits (see target-ppc/translate.c gen_conditional_store).

The user-mode store conditional code erroneously extracts the size by ANDing
with a 4 bit mask; this breaks if size >= 16.

Eliminate the mask to make the extraction of size mirror its encoding.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-05-29 09:12:24 -05:00 committed by Alexander Graf
parent f46e9a0b99
commit 4b1daa72d3
1 changed files with 1 additions and 1 deletions
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linux-user/main.c
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@ -1497,7 +1497,7 @@ static int do_store_exclusive(CPUPPCState *env)
segv = 1;
} else {
int reg = env->reserve_info & 0x1f;
int size = (env->reserve_info >> 5) & 0xf;
int size = env->reserve_info >> 5;
int stored = 0;
if (addr == env->reserve_addr) {