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target-i386: fix ARPL 

The arpl implementation in target-i386/translate.c uses cpu_A0
temporary across a brcond op.  This patch fixes that issue.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Laurent Desnogues 2009-10-06 10:14:29 +02:00 committed by Aurelien Jarno
parent d9ace8b384
commit 49d9fdcca6
1 changed files with 7 additions and 3 deletions
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10
target-i386/translate.c
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@ -7305,7 +7305,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
#endif #endif
{ {
int label1; int label1;
TCGv t0, t1, t2; TCGv t0, t1, t2, a0;
if (!s->pe || s->vm86) if (!s->pe || s->vm86)
goto illegal_op; goto illegal_op;
@ -7320,8 +7320,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
a0 = tcg_temp_local_new();
tcg_gen_mov_tl(a0, cpu_A0);
} else { } else {
gen_op_mov_v_reg(ot, t0, rm); gen_op_mov_v_reg(ot, t0, rm);
TCGV_UNUSED(a0);
} }
gen_op_mov_v_reg(ot, t1, reg); gen_op_mov_v_reg(ot, t1, reg);
tcg_gen_andi_tl(cpu_tmp0, t0, 3); tcg_gen_andi_tl(cpu_tmp0, t0, 3);
@ -7334,8 +7337,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
tcg_gen_movi_tl(t2, CC_Z); tcg_gen_movi_tl(t2, CC_Z);
gen_set_label(label1); gen_set_label(label1);
if (mod != 3) { if (mod != 3) {
gen_op_st_v(ot + s->mem_index, t0, cpu_A0); gen_op_st_v(ot + s->mem_index, t0, a0);
} else { tcg_temp_free(a0);
} else {
gen_op_mov_reg_v(ot, rm, t0); gen_op_mov_reg_v(ot, rm, t0);
} }
if (s->cc_op != CC_OP_DYNAMIC) if (s->cc_op != CC_OP_DYNAMIC)