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target/arm: Make VTOR register banked for v8M 

Make the VTOR register banked if v8M security extensions are enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-09-07 13:54:53 +01:00
parent f104919d15
commit 45db7ba681
4 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
hw/intc/armv7m_nvic.c
View File

@ -403,7 +403,7 @@ static void set_irq_level(void *opaque, int n, int level)
} }
} }
static uint32_t nvic_readl(NVICState *s, uint32_t offset) static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
{ {
ARMCPU *cpu = s->cpu; ARMCPU *cpu = s->cpu;
uint32_t val; uint32_t val;
@ -441,7 +441,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
/* ISRPREEMPT not implemented */ /* ISRPREEMPT not implemented */
return val; return val;
case 0xd08: /* Vector Table Offset. */ case 0xd08: /* Vector Table Offset. */
return cpu->env.v7m.vecbase; return cpu->env.v7m.vecbase[attrs.secure];
case 0xd0c: /* Application Interrupt/Reset Control. */ case 0xd0c: /* Application Interrupt/Reset Control. */
return 0xfa050000 | (s->prigroup << 8); return 0xfa050000 | (s->prigroup << 8);
case 0xd10: /* System Control. */ case 0xd10: /* System Control. */
@ -617,7 +617,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
} }
} }
static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
MemTxAttrs attrs)
{ {
ARMCPU *cpu = s->cpu; ARMCPU *cpu = s->cpu;
@ -638,7 +639,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
} }
break; break;
case 0xd08: /* Vector Table Offset. */ case 0xd08: /* Vector Table Offset. */
cpu->env.v7m.vecbase = value & 0xffffff80; cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
break; break;
case 0xd0c: /* Application Interrupt/Reset Control. */ case 0xd0c: /* Application Interrupt/Reset Control. */
if ((value >> 16) == 0x05fa) { if ((value >> 16) == 0x05fa) {
@ -944,7 +945,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
break; break;
default: default:
if (size == 4) { if (size == 4) {
val = nvic_readl(s, offset); val = nvic_readl(s, offset, attrs);
} else { } else {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"NVIC: Bad read of size %d at offset 0x%x\n", "NVIC: Bad read of size %d at offset 0x%x\n",
@ -1025,7 +1026,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
return MEMTX_OK; return MEMTX_OK;
} }
if (size == 4) { if (size == 4) {
nvic_writel(s, offset, value); nvic_writel(s, offset, value, attrs);
return MEMTX_OK; return MEMTX_OK;
} }
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,

2
target/arm/cpu.h
View File

@ -420,7 +420,7 @@ typedef struct CPUARMState {
struct { struct {
uint32_t other_sp; uint32_t other_sp;
uint32_t vecbase; uint32_t vecbase[2];
uint32_t basepri[2]; uint32_t basepri[2];
uint32_t control[2]; uint32_t control[2];
uint32_t ccr; /* Configuration and Control */ uint32_t ccr; /* Configuration and Control */

2
target/arm/helper.c
View File

@ -6067,7 +6067,7 @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu)
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
MemTxResult result; MemTxResult result;
hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4;
uint32_t addr; uint32_t addr;
addr = address_space_ldl(cs->as, vec, addr = address_space_ldl(cs->as, vec,

3
target/arm/machine.c
View File

@ -114,7 +114,7 @@ static const VMStateDescription vmstate_m = {
.minimum_version_id = 4, .minimum_version_id = 4,
.needed = m_needed, .needed = m_needed,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
VMSTATE_UINT32(env.v7m.ccr, ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
@ -254,6 +254,7 @@ static const VMStateDescription vmstate_m_security = {
VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };