mirror of https://github.com/xqemu/xqemu.git
added support for direct patching on i386 host (faster emulation) - increased translation buffer size - added new TLB support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@517 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
ecd854fdb4
commit
4390df5107
137
exec-all.h
137
exec-all.h
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@ -28,6 +28,11 @@
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#define tostring(s) #s
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#endif
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#ifndef THUNK_H
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/* horrible */
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typedef uint32_t target_ulong;
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#endif
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#if GCC_MAJOR < 3
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#define __builtin_expect(x, n) (x)
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#endif
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@ -77,10 +82,12 @@ int cpu_restore_state(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc);
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void cpu_exec_init(void);
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int page_unprotect(unsigned long address);
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void tb_invalidate_page(unsigned long address);
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void tb_invalidate_page_range(target_ulong start, target_ulong end);
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void tlb_flush_page(CPUState *env, uint32_t addr);
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void tlb_flush_page_write(CPUState *env, uint32_t addr);
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void tlb_flush(CPUState *env);
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int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
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int is_user, int is_softmmu);
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#define CODE_GEN_MAX_SIZE 65536
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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@ -88,11 +95,47 @@ void tlb_flush(CPUState *env);
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#define CODE_GEN_HASH_BITS 15
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#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
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#define CODE_GEN_PHYS_HASH_BITS 15
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#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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/* maximum total translate dcode allocated */
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#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
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/* NOTE: the translated code area cannot be too big because on some
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archs the range of "fast" function calls are limited. Here is a
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summary of the ranges:
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i386 : signed 32 bits
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arm : signed 26 bits
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ppc : signed 24 bits
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sparc : signed 32 bits
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alpha : signed 23 bits
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*/
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#if defined(__alpha__)
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#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
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#elif defined(__powerpc__)
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#define CODE_GEN_BUFFER_SIZE (6 * 1024)
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#else
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#define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
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#endif
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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#if defined(__powerpc__)
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/* estimated block size for TB allocation */
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/* XXX: use a per code average code fragment size and modulate it
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according to the host CPU */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 128
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#else
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#define CODE_GEN_AVG_BLOCK_SIZE 64
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#endif
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#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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#if defined(__powerpc__)
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#define USE_DIRECT_JUMP
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#endif
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#if defined(__i386__)
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#define USE_DIRECT_JUMP
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#endif
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@ -103,8 +146,14 @@ typedef struct TranslationBlock {
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint8_t *tc_ptr; /* pointer to the translated code */
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struct TranslationBlock *hash_next; /* next matching block */
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struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
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struct TranslationBlock *hash_next; /* next matching tb for virtual address */
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/* next matching tb for physical address. */
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struct TranslationBlock *phys_hash_next;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2];
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target_ulong page_addr[2];
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/* the following data are used to directly call another TB from
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the code of this one. */
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uint16_t tb_next_offset[2]; /* offset of original jump target */
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@ -126,11 +175,19 @@ static inline unsigned int tb_hash_func(unsigned long pc)
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return pc & (CODE_GEN_HASH_SIZE - 1);
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}
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static inline unsigned int tb_phys_hash_func(unsigned long pc)
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{
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return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
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}
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TranslationBlock *tb_alloc(unsigned long pc);
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void tb_flush(CPUState *env);
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void tb_link(TranslationBlock *tb);
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void tb_link_phys(TranslationBlock *tb,
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target_ulong phys_pc, target_ulong phys_page2);
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extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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extern uint8_t *code_gen_ptr;
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@ -159,8 +216,10 @@ static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
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return NULL;
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}
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#if defined(__powerpc__)
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#if defined(USE_DIRECT_JUMP)
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#if defined(__powerpc__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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{
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uint32_t val, *ptr;
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@ -177,6 +236,14 @@ static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#elif defined(__i386__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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{
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitely */
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}
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#endif
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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@ -223,7 +290,7 @@ TranslationBlock *tb_find_pc(unsigned long pc_ptr);
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#if defined(__powerpc__)
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/* on PowerPC we patch the jump instruction directly */
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/* we patch the jump instruction directly */
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#define JUMP_TB(opname, tbparam, n, eip)\
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do {\
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asm volatile (".section \".data\"\n"\
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@ -239,7 +306,28 @@ do {\
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#define JUMP_TB2(opname, tbparam, n)\
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do {\
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asm volatile ("b __op_jmp%0\n" : : "i" (n + 2));\
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asm volatile ("b __op_jmp" #n "\n");\
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} while (0)
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#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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/* we patch the jump instruction directly */
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#define JUMP_TB(opname, tbparam, n, eip)\
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do {\
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asm volatile (".section \".data\"\n"\
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"__op_label" #n "." stringify(opname) ":\n"\
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".long 1f\n"\
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".previous\n"\
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"jmp __op_jmp" #n "\n"\
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"1:\n");\
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T0 = (long)(tbparam) + (n);\
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EIP = eip;\
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EXIT_TB();\
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} while (0)
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#define JUMP_TB2(opname, tbparam, n)\
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do {\
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asm volatile ("jmp __op_jmp" #n "\n");\
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} while (0)
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#else
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@ -261,19 +349,11 @@ dummy_label ## n:\
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/* second jump to same destination 'n' */
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#define JUMP_TB2(opname, tbparam, n)\
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do {\
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goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
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goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
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} while (0)
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#endif
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/* physical memory access */
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#define IO_MEM_NB_ENTRIES 256
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#define TLB_INVALID_MASK (1 << 3)
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#define IO_MEM_SHIFT 4
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#define IO_MEM_UNASSIGNED (1 << IO_MEM_SHIFT)
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unsigned long physpage_find(unsigned long page);
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extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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@ -441,3 +521,26 @@ void tlb_fill(unsigned long addr, int is_write, int is_user,
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#undef env
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#endif
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#if defined(CONFIG_USER_ONLY)
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static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
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{
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return addr;
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}
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#else
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/* NOTE: this function can trigger an exception */
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/* XXX: i386 target specific */
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static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
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{
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int is_user, index;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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is_user = ((env->hflags & HF_CPL_MASK) == 3);
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if (__builtin_expect(env->tlb_read[is_user][index].address !=
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(addr & TARGET_PAGE_MASK), 0)) {
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ldub_code((void *)addr);
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}
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return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
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}
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#endif
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