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RISC-V: Remove unused class definitions 

Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Michael Clark 2018-03-04 13:27:37 +13:00
parent b7938980fb
commit 42b3a4b7cc
No known key found for this signature in database
GPG Key ID: 6BF1D7B357EF3E4F
9 changed files with 0 additions and 123 deletions
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6
hw/riscv/riscv_hart.c
View File

@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, void *data)
dc->realize = riscv_harts_realize;
}
static void riscv_harts_init(Object *obj)
{
/* RISCVHartArrayState *s = SIFIVE_COREPLEX(obj); */
}
static const TypeInfo riscv_harts_info = {
.name = TYPE_RISCV_HART_ARRAY,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(RISCVHartArrayState),
.instance_init = riscv_harts_init,
.class_init = riscv_harts_class_init,
};

25
hw/riscv/sifive_e.c
View File

@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev)
{
return 0;
}
static void riscv_sifive_e_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = riscv_sifive_e_sysbus_device_init;
}
static const TypeInfo riscv_sifive_e_device = {
.name = TYPE_SIFIVE_E,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SiFiveEState),
.class_init = riscv_sifive_e_class_init,
};
static void riscv_sifive_e_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive E SDK";
@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
static void riscv_sifive_e_register_types(void)
{
type_register_static(&riscv_sifive_e_device);
}
type_init(riscv_sifive_e_register_types);

25
hw/riscv/sifive_u.c
View File

@ -301,31 +301,6 @@ static void riscv_sifive_u_init(MachineState *machine)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
}
static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
{
return 0;
}
static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = riscv_sifive_u_sysbus_device_init;
}
static const TypeInfo riscv_sifive_u_device = {
.name = TYPE_SIFIVE_U,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SiFiveUState),
.class_init = riscv_sifive_u_class_init,
};
static void riscv_sifive_u_register_types(void)
{
type_register_static(&riscv_sifive_u_device);
}
type_init(riscv_sifive_u_register_types);
static void riscv_sifive_u_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive U SDK";

20
hw/riscv/spike.c
View File

@ -334,18 +334,6 @@ static void spike_v1_09_1_board_init(MachineState *machine)
smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
}
static const TypeInfo spike_v_1_09_1_device = {
.name = TYPE_RISCV_SPIKE_V1_09_1_BOARD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SpikeState),
};
static const TypeInfo spike_v_1_10_0_device = {
.name = TYPE_RISCV_SPIKE_V1_10_0_BOARD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SpikeState),
};
static void spike_v1_09_1_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
@ -363,11 +351,3 @@ static void spike_v1_10_0_machine_init(MachineClass *mc)
DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
static void riscv_spike_board_register_types(void)
{
type_register_static(&spike_v_1_09_1_device);
type_register_static(&spike_v_1_10_0_device);
}
type_init(riscv_spike_board_register_types);

25
hw/riscv/virt.c
View File

@ -382,24 +382,6 @@ static void riscv_virt_board_init(MachineState *machine)
serial_hd(0), DEVICE_LITTLE_ENDIAN);
}
static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev)
{
return 0;
}
static void riscv_virt_board_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = riscv_virt_board_sysbus_device_init;
}
static const TypeInfo riscv_virt_board_device = {
.name = TYPE_RISCV_VIRT_BOARD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(RISCVVirtState),
.class_init = riscv_virt_board_class_init,
};
static void riscv_virt_board_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
@ -408,10 +390,3 @@ static void riscv_virt_board_machine_init(MachineClass *mc)
}
DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
static void riscv_virt_board_register_types(void)
{
type_register_static(&riscv_virt_board_device);
}
type_init(riscv_virt_board_register_types);

5
include/hw/riscv/sifive_e.h
View File

@ -19,11 +19,6 @@
#ifndef HW_SIFIVE_E_H
#define HW_SIFIVE_E_H
#define TYPE_SIFIVE_E "riscv.sifive_e"
#define SIFIVE_E(obj) \
OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E)
typedef struct SiFiveEState {
/*< private >*/
SysBusDevice parent_obj;

5
include/hw/riscv/sifive_u.h
View File

@ -19,11 +19,6 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
#define TYPE_SIFIVE_U "riscv.sifive_u"
#define SIFIVE_U(obj) \
OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U)
typedef struct SiFiveUState {
/*< private >*/
SysBusDevice parent_obj;

7
include/hw/riscv/spike.h
View File

@ -19,12 +19,6 @@
#ifndef HW_SPIKE_H
#define HW_SPIKE_H
#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1"
#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10"
#define SPIKE(obj) \
OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD)
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
@ -35,7 +29,6 @@ typedef struct {
int fdt_size;
} SpikeState;
enum {
SPIKE_MROM,
SPIKE_CLINT,

5
include/hw/riscv/virt.h
View File

@ -19,10 +19,6 @@
#ifndef HW_VIRT_H
#define HW_VIRT_H
#define TYPE_RISCV_VIRT_BOARD "riscv.virt"
#define VIRT(obj) \
OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
@ -45,7 +41,6 @@ enum {
VIRT_DRAM
};
enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */