mirror of https://github.com/xqemu/xqemu.git
xilinx-next-2018-06-15.for-upstream
-----BEGIN PGP SIGNATURE----- iQEcBAABCAAGBQJbI84PAAoJECnFlngPa8qD3cAIAJomdBvSh8SQP9hCHyjVn0Ks vHvcpuB7PvtezXvj8ibaLqbHQtJAL9Wxghsfj8EtQSbbXMw8Ndbb9bcIpBY87W6C YtgcJ9sZOw6ya16AmEbti5Qm9GSrzhMRyYhRORqrViOmxJQrbXRboXx73QGog/10 S6LPBfsQT3LI4V6IOvqKsjPnTVTzHsv3l+IYEGA74W05OxvTehYpIek0g/D0o+Ul TgsbQJWbUDaTwyDsn6GXd6buoD0QBJa6aLLuDIbes0dJq7EIi4fTutXvErTHC+wg Mzvec6Xg8dSHuoHsQlVzk8MFHnHOL6Dlty1hP4ydhri93GBDCJGND/YZQpZqELw= =oKzf -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-06-15.for-upstream' into staging xilinx-next-2018-06-15.for-upstream # gpg: Signature made Fri 15 Jun 2018 15:32:47 BST # gpg: using RSA key 29C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2018-06-15.for-upstream: target-microblaze: Rework NOP/zero instruction handling target-microblaze: mmu: Correct masking of output addresses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
42747d6abb
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@ -159,7 +159,6 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
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lu->vaddr = tlb_tag;
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lu->paddr = tlb_rpn & mmu->c_addr_mask;
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lu->paddr = tlb_rpn;
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lu->size = tlb_size;
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lu->err = ERR_HIT;
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lu->idx = i;
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@ -90,7 +90,6 @@ typedef struct DisasContext {
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uint32_t jmp_pc;
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int abort_at_next_insn;
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int nr_nops;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext;
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@ -1576,17 +1575,12 @@ static inline void decode(DisasContext *dc, uint32_t ir)
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dc->ir = ir;
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LOG_DIS("%8.8x\t", dc->ir);
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if (dc->ir)
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dc->nr_nops = 0;
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else {
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if (ir == 0) {
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trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
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LOG_DIS("nr_nops=%d\t", dc->nr_nops);
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dc->nr_nops++;
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if (dc->nr_nops > 4) {
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cpu_abort(CPU(dc->cpu), "fetching nop sequence\n");
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}
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/* Don't decode nop/zero instructions any further. */
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return;
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}
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/* bit 2 seems to indicate insn type. */
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dc->type_b = ir & (1 << 29);
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@ -1633,7 +1627,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->cpustate_changed = 0;
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dc->abort_at_next_insn = 0;
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dc->nr_nops = 0;
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if (pc_start & 3) {
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cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
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