mirror of https://github.com/xqemu/xqemu.git
apb: move the two secondary PCI bridges objects into APBState
This enables us to remove these parameters from pci_apb_init(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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@ -612,8 +612,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
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}
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}
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APBState *pci_apb_init(hwaddr special_base,
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APBState *pci_apb_init(hwaddr special_base,
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hwaddr mem_base,
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hwaddr mem_base)
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PCIBus **busA, PCIBus **busB)
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{
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{
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DeviceState *dev;
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DeviceState *dev;
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SysBusDevice *s;
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SysBusDevice *s;
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@ -621,7 +620,6 @@ APBState *pci_apb_init(hwaddr special_base,
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APBState *d;
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APBState *d;
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IOMMUState *is;
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IOMMUState *is;
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PCIDevice *pci_dev;
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PCIDevice *pci_dev;
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PCIBridge *br;
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/* Ultrasparc PBM main bus */
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/* Ultrasparc PBM main bus */
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dev = qdev_create(NULL, TYPE_APB);
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dev = qdev_create(NULL, TYPE_APB);
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@ -659,18 +657,16 @@ APBState *pci_apb_init(hwaddr special_base,
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/* APB secondary busses */
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/* APB secondary busses */
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
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TYPE_PBM_PCI_BRIDGE);
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TYPE_PBM_PCI_BRIDGE);
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br = PCI_BRIDGE(pci_dev);
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d->bridgeB = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(br, "pciB", pci_pbm_map_irq);
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pci_bridge_map_irq(d->bridgeB, "pciB", pci_pbm_map_irq);
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qdev_init_nofail(&pci_dev->qdev);
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qdev_init_nofail(&pci_dev->qdev);
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*busB = pci_bridge_get_sec_bus(br);
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
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TYPE_PBM_PCI_BRIDGE);
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TYPE_PBM_PCI_BRIDGE);
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br = PCI_BRIDGE(pci_dev);
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d->bridgeA = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(br, "pciA", pci_pbm_map_irq);
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pci_bridge_map_irq(d->bridgeA, "pciA", pci_pbm_map_irq);
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qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
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qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
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qdev_init_nofail(&pci_dev->qdev);
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qdev_init_nofail(&pci_dev->qdev);
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*busA = pci_bridge_get_sec_bus(br);
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return d;
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return d;
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}
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}
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@ -27,6 +27,7 @@
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#include "cpu.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci-host/apb.h"
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#include "hw/pci-host/apb.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/pc.h"
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@ -501,7 +502,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
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prom_init(hwdef->prom_addr, bios_name);
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prom_init(hwdef->prom_addr, bios_name);
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apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, &pci_busA, &pci_busB);
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apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE);
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/* Wire up PCI interrupts to CPU */
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/* Wire up PCI interrupts to CPU */
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for (i = 0; i < IVEC_MAX; i++) {
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for (i = 0; i < IVEC_MAX; i++) {
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@ -510,6 +511,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
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}
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}
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pci_bus = PCI_HOST_BRIDGE(apb)->bus;
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pci_bus = PCI_HOST_BRIDGE(apb)->bus;
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pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
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pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
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/* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
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/* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
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reserved (leaving no slots free after on-board devices) however slots
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reserved (leaving no slots free after on-board devices) however slots
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@ -68,6 +68,8 @@ typedef struct APBState {
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MemoryRegion pci_ioport;
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MemoryRegion pci_ioport;
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uint64_t pci_irq_in;
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uint64_t pci_irq_in;
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IOMMUState iommu;
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IOMMUState iommu;
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PCIBridge *bridgeA;
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PCIBridge *bridgeB;
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uint32_t pci_control[16];
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t pci_irq_map[8];
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uint32_t pci_err_irq_map[4];
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uint32_t pci_err_irq_map[4];
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@ -92,6 +94,5 @@ typedef struct PBMPCIBridge {
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OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
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OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
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APBState *pci_apb_init(hwaddr special_base,
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APBState *pci_apb_init(hwaddr special_base,
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hwaddr mem_base,
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hwaddr mem_base);
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PCIBus **bus2, PCIBus **bus3);
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#endif
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#endif
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