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net: xilinx_ethlite: Fix Rx-pong interrupt 

There is no CTRL_I bit in the pong buffer control register. The
CTRL_I bit from the ping buffer masks both ping and pong buffers.
Fix.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Peter Crosthwaite 2014-05-05 21:39:38 -07:00 committed by Stefan Hajnoczi
parent 959e41473f
commit 40e76f736d
1 changed files with 2 additions and 1 deletions
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3
hw/net/xilinx_ethlite.c
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@ -196,8 +196,9 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
s->regs[rxbase + R_RX_CTRL0] |= CTRL_S; s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I) if (s->regs[R_RX_CTRL0] & CTRL_I) {
eth_pulse_irq(s); eth_pulse_irq(s);
}
/* If c_rx_pingpong was set flip buffers. */ /* If c_rx_pingpong was set flip buffers. */
s->rxbuf ^= s->c_rx_pingpong; s->rxbuf ^= s->c_rx_pingpong;