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q35: update lpc pci config space according to configured devices 

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Gerd Hoffmann 2012-11-23 15:02:18 +01:00
parent c177684c75
commit 3f5bc9e8af
3 changed files with 30 additions and 12 deletions
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1
hw/ich9.h
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@ -51,6 +51,7 @@ typedef struct ICH9LPCState {
/* isa bus */ /* isa bus */
ISABus *isa_bus; ISABus *isa_bus;
MemoryRegion rbca_mem; MemoryRegion rbca_mem;
Notifier machine_ready;
qemu_irq *pic; qemu_irq *pic;
qemu_irq *ioapic; qemu_irq *ioapic;

29
hw/lpc_ich9.c
View File

@ -60,6 +60,7 @@
#include "pam.h" #include "pam.h"
#include "pci_internals.h" #include "pci_internals.h"
#include "exec-memory.h" #include "exec-memory.h"
#include "sysemu.h"
static int ich9_lpc_sci_irq(ICH9LPCState *lpc); static int ich9_lpc_sci_irq(ICH9LPCState *lpc);
@ -456,6 +457,30 @@ static const MemoryRegionOps rbca_mmio_ops = {
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
}; };
static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
{
ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
uint8_t *pci_conf;
pci_conf = s->d.config;
if (isa_is_ioport_assigned(0x3f8)) {
/* com1 */
pci_conf[0x82] |= 0x01;
}
if (isa_is_ioport_assigned(0x2f8)) {
/* com2 */
pci_conf[0x82] |= 0x02;
}
if (isa_is_ioport_assigned(0x378)) {
/* lpt */
pci_conf[0x82] |= 0x04;
}
if (isa_is_ioport_assigned(0x3f0)) {
/* floppy */
pci_conf[0x82] |= 0x08;
}
}
static int ich9_lpc_initfn(PCIDevice *d) static int ich9_lpc_initfn(PCIDevice *d)
{ {
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
@ -473,6 +498,10 @@ static int ich9_lpc_initfn(PCIDevice *d)
ich9_cc_init(lpc); ich9_cc_init(lpc);
apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc); apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
lpc->machine_ready.notify = ich9_lpc_machine_ready;
qemu_add_machine_init_done_notifier(&lpc->machine_ready);
return 0; return 0;
} }

12
hw/smbus_ich9.c
View File

@ -77,18 +77,6 @@ static int ich9_smbus_initfn(PCIDevice *d)
/* TODO? D31IP.SMIP in chipset configuration space */ /* TODO? D31IP.SMIP in chipset configuration space */
pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */ pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
/*
* update parameters based on
* paralell_hds[0]
* serial_hds[0]
* serial_hds[0]
* fdc
*
* Is there any OS that depends on them?
*/
pci_set_byte(d->config + ICH9_SMB_HOSTC, 0); pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
/* TODO bar0, bar1: 64bit BAR support*/ /* TODO bar0, bar1: 64bit BAR support*/