mirror of https://github.com/xqemu/xqemu.git
target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move the reset code over to the class reset function and have cpu_state_reset simply do a reset on the CPU QOM object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Peter Maydell
parent
caa1d0779e
commit
3c30dd5a68
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@ -20,18 +20,106 @@
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#include "cpu-qom.h"
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#include "cpu-qom.h"
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#include "qemu-common.h"
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#include "qemu-common.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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/* CPUClass::reset() */
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s)
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static void arm_cpu_reset(CPUState *s)
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{
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{
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ARMCPU *cpu = ARM_CPU(s);
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ARMCPU *cpu = ARM_CPU(s);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
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CPUARMState *env = &cpu->env;
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uint32_t tmp = 0;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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log_cpu_state(env, 0);
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}
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acc->parent_reset(s);
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acc->parent_reset(s);
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/* TODO Inline the current contents of cpu_state_reset(),
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tmp = env->cp15.c15_config_base_address;
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once cpu_reset_model_id() is eliminated. */
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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cpu_state_reset(&cpu->env);
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env->cp15.c15_config_base_address = tmp;
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env->cp15.c0_cpuid = cpu->midr;
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->cp15.c0_cachetype = cpu->ctr;
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env->cp15.c1_sys = cpu->reset_sctlr;
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env->cp15.c0_c1[0] = cpu->id_pfr0;
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env->cp15.c0_c1[1] = cpu->id_pfr1;
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env->cp15.c0_c1[2] = cpu->id_dfr0;
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env->cp15.c0_c1[3] = cpu->id_afr0;
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env->cp15.c0_c1[4] = cpu->id_mmfr0;
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env->cp15.c0_c1[5] = cpu->id_mmfr1;
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env->cp15.c0_c1[6] = cpu->id_mmfr2;
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env->cp15.c0_c1[7] = cpu->id_mmfr3;
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env->cp15.c0_c2[0] = cpu->id_isar0;
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env->cp15.c0_c2[1] = cpu->id_isar1;
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env->cp15.c0_c2[2] = cpu->id_isar2;
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env->cp15.c0_c2[3] = cpu->id_isar3;
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env->cp15.c0_c2[4] = cpu->id_isar4;
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env->cp15.c0_c2[5] = cpu->id_isar5;
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env->cp15.c15_i_min = 0xff0;
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env->cp15.c0_clid = cpu->clidr;
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memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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}
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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env->cp15.c15_cpar = 1;
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}
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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if (IS_M(env)) {
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uint32_t pc;
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uint8_t *rom;
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env->uncached_cpsr &= ~CPSR_I;
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rom = rom_ptr(0);
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if (rom) {
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom);
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pc = ldl_p(rom + 4);
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env->thumb = pc & 1;
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env->regs[15] = pc & ~1;
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}
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}
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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env->cp15.c2_base_mask = 0xffffc000u;
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/* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement no event counters.
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*/
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env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.standard_fp_status);
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env);
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}
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}
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static inline void set_feature(CPUARMState *env, int feature)
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static inline void set_feature(CPUARMState *env, int feature)
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@ -2,106 +2,11 @@
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#include "gdbstub.h"
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#include "gdbstub.h"
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#include "helper.h"
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#include "helper.h"
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#include "host-utils.h"
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#include "host-utils.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "sysemu.h"
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#include "sysemu.h"
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/* TODO Move contents into arm_cpu_reset() in cpu.c,
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* once cpu_reset_model_id() is eliminated,
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* and then forward to cpu_reset() here.
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*/
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void cpu_state_reset(CPUARMState *env)
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void cpu_state_reset(CPUARMState *env)
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{
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{
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uint32_t tmp = 0;
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cpu_reset(ENV_GET_CPU(env));
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ARMCPU *cpu = arm_env_get_cpu(env);
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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log_cpu_state(env, 0);
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}
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tmp = env->cp15.c15_config_base_address;
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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env->cp15.c15_config_base_address = tmp;
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env->cp15.c0_cpuid = cpu->midr;
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->cp15.c0_cachetype = cpu->ctr;
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env->cp15.c1_sys = cpu->reset_sctlr;
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env->cp15.c0_c1[0] = cpu->id_pfr0;
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env->cp15.c0_c1[1] = cpu->id_pfr1;
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env->cp15.c0_c1[2] = cpu->id_dfr0;
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env->cp15.c0_c1[3] = cpu->id_afr0;
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env->cp15.c0_c1[4] = cpu->id_mmfr0;
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env->cp15.c0_c1[5] = cpu->id_mmfr1;
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env->cp15.c0_c1[6] = cpu->id_mmfr2;
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env->cp15.c0_c1[7] = cpu->id_mmfr3;
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env->cp15.c0_c2[0] = cpu->id_isar0;
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env->cp15.c0_c2[1] = cpu->id_isar1;
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env->cp15.c0_c2[2] = cpu->id_isar2;
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env->cp15.c0_c2[3] = cpu->id_isar3;
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env->cp15.c0_c2[4] = cpu->id_isar4;
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env->cp15.c0_c2[5] = cpu->id_isar5;
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env->cp15.c15_i_min = 0xff0;
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env->cp15.c0_clid = cpu->clidr;
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memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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}
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#if defined (CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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env->cp15.c15_cpar = 1;
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}
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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if (IS_M(env)) {
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uint32_t pc;
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uint8_t *rom;
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env->uncached_cpsr &= ~CPSR_I;
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rom = rom_ptr(0);
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if (rom) {
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom);
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pc = ldl_p(rom + 4);
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env->thumb = pc & 1;
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env->regs[15] = pc & ~1;
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}
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}
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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env->cp15.c2_base_mask = 0xffffc000u;
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/* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement no event counters.
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*/
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env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.standard_fp_status);
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env);
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}
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}
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static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
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static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
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