mirror of https://github.com/xqemu/xqemu.git
hw/intc/arm_gicv3_its: Implement ITS base class
This is the basic skeleton for both KVM and software-emulated ITS. Since we already prepare status structure, we also introduce complete VMState description. But, because we currently have no migratable implementations, we also set unmigratable flag. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Pavel Fedin
Peter Maydell
parent
d19a4d4ef4
commit
386ce3c7fc
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@ -16,6 +16,7 @@ common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
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common-obj-$(CONFIG_OPENPIC) += openpic.o
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common-obj-$(CONFIG_OPENPIC) += openpic.o
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obj-$(CONFIG_APIC) += apic.o apic_common.o
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obj-$(CONFIG_APIC) += apic.o apic_common.o
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@ -0,0 +1,148 @@
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/*
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* ITS base class for a GICv3-based system
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Pavel Fedin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/msi.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "qemu/log.h"
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static void gicv3_its_pre_save(void *opaque)
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{
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GICv3ITSState *s = (GICv3ITSState *)opaque;
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GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
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if (c->pre_save) {
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c->pre_save(s);
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}
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}
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static int gicv3_its_post_load(void *opaque, int version_id)
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{
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GICv3ITSState *s = (GICv3ITSState *)opaque;
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GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
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if (c->post_load) {
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c->post_load(s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_its = {
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.name = "arm_gicv3_its",
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.pre_save = gicv3_its_pre_save,
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.post_load = gicv3_its_post_load,
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.unmigratable = true,
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};
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static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
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return MEMTX_ERROR;
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}
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static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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if (offset == 0x0040 && ((size == 2) || (size == 4))) {
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
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GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
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int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
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if (ret <= 0) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ITS: Error sending MSI: %s\n", strerror(-ret));
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return MEMTX_DECODE_ERROR;
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}
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return MEMTX_OK;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ITS write at bad offset 0x%"PRIx64"\n", offset);
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return MEMTX_DECODE_ERROR;
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}
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}
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static const MemoryRegionOps gicv3_its_trans_ops = {
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.read_with_attrs = gicv3_its_trans_read,
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.write_with_attrs = gicv3_its_trans_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
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"control", ITS_CONTROL_SIZE);
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memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
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&gicv3_its_trans_ops, s,
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"translation", ITS_TRANS_SIZE);
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/* Our two regions are always adjacent, therefore we now combine them
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* into a single one in order to make our users' life easier.
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*/
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memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
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memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
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memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
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&s->iomem_its_translation);
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sysbus_init_mmio(sbd, &s->iomem_main);
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msi_nonbroken = true;
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}
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static void gicv3_its_common_reset(DeviceState *dev)
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{
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
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s->ctlr = 0;
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s->cbaser = 0;
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s->cwriter = 0;
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s->creadr = 0;
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memset(&s->baser, 0, sizeof(s->baser));
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gicv3_its_post_load(s, 0);
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}
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static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = gicv3_its_common_reset;
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dc->vmsd = &vmstate_its;
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}
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static const TypeInfo gicv3_its_common_info = {
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.name = TYPE_ARM_GICV3_ITS_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GICv3ITSState),
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.class_size = sizeof(GICv3ITSCommonClass),
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.class_init = gicv3_its_common_class_init,
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.abstract = true,
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};
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static void gicv3_its_common_register_types(void)
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{
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type_register_static(&gicv3_its_common_info);
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}
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type_init(gicv3_its_common_register_types)
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@ -0,0 +1,78 @@
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/*
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* ITS support for ARM GICv3
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Pavel Fedin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_ARM_GICV3_ITS_COMMON_H
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#define QEMU_ARM_GICV3_ITS_COMMON_H
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#include "hw/sysbus.h"
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#include "hw/intc/arm_gicv3_common.h"
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#define ITS_CONTROL_SIZE 0x10000
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#define ITS_TRANS_SIZE 0x10000
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#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
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struct GICv3ITSState {
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SysBusDevice parent_obj;
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MemoryRegion iomem_main;
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MemoryRegion iomem_its_cntrl;
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MemoryRegion iomem_its_translation;
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GICv3State *gicv3;
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int dev_fd; /* kvm device fd if backed by kvm vgic support */
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uint64_t gits_translater_gpa;
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bool translater_gpa_known;
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/* Registers */
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uint32_t ctlr;
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uint64_t cbaser;
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uint64_t cwriter;
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uint64_t creadr;
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uint64_t baser[8];
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Error *migration_blocker;
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};
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typedef struct GICv3ITSState GICv3ITSState;
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void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
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#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
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#define ARM_GICV3_ITS_COMMON(obj) \
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OBJECT_CHECK(GICv3ITSState, (obj), TYPE_ARM_GICV3_ITS_COMMON)
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#define ARM_GICV3_ITS_COMMON_CLASS(klass) \
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OBJECT_CLASS_CHECK(GICv3ITSCommonClass, (klass), TYPE_ARM_GICV3_ITS_COMMON)
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#define ARM_GICV3_ITS_COMMON_GET_CLASS(obj) \
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OBJECT_GET_CLASS(GICv3ITSCommonClass, (obj), TYPE_ARM_GICV3_ITS_COMMON)
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struct GICv3ITSCommonClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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int (*send_msi)(GICv3ITSState *s, uint32_t data, uint16_t devid);
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void (*pre_save)(GICv3ITSState *s);
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void (*post_load)(GICv3ITSState *s);
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};
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typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
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#endif
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@ -255,4 +255,23 @@ struct kvm_guest_debug_arch;
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void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
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void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
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/**
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* its_class_name
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*
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* Return the ITS class name to use depending on whether KVM acceleration
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* and KVM CAP_SIGNAL_MSI are supported
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*
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* Returns: class name to use or NULL
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*/
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static inline const char *its_class_name(void)
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{
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if (kvm_irqchip_in_kernel()) {
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/* KVM implementation requires this capability */
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return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
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} else {
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/* Software emulation is not implemented yet */
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return NULL;
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}
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}
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#endif
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#endif
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