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sh7750: Change cpu field type to SuperHCPU 

This brings us a step closer to QOM'ified SH7750 SoC and
fixes b350ab75 (target-sh4: Move PVR/PRR/CVR into SuperHCPUClass)
assuming SuperHCPU type for SUPERH_CPU_GET_CLASS().

Fix Coding Style issues while at it (indentation, braces).

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Andreas Färber 2013-04-09 16:51:24 +02:00 committed by Aurelien Jarno
parent 06f3ed2698
commit 2f493fee18
4 changed files with 52 additions and 51 deletions
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2
hw/sh4/r2d.c
View File

@ -258,7 +258,7 @@ static void r2d_init(QEMUMachineInitArgs *args)
vmstate_register_ram_global(sdram); vmstate_register_ram_global(sdram);
memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
/* Register peripherals */ /* Register peripherals */
s = sh7750_init(env, address_space_mem); s = sh7750_init(cpu, address_space_mem);
irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
dev = qdev_create(NULL, "sh_pci"); dev = qdev_create(NULL, "sh_pci");

75
hw/sh4/sh7750.c
View File

@ -44,7 +44,7 @@ typedef struct SH7750State {
MemoryRegion iomem_ffc; MemoryRegion iomem_ffc;
MemoryRegion mmct_iomem; MemoryRegion mmct_iomem;
/* CPU */ /* CPU */
CPUSH4State *cpu; SuperHCPU *cpu;
/* Peripheral frequency in Hz */ /* Peripheral frequency in Hz */
uint32_t periph_freq; uint32_t periph_freq;
/* SDRAM controller */ /* SDRAM controller */
@ -79,7 +79,7 @@ typedef struct SH7750State {
static inline int has_bcr3_and_bcr4(SH7750State * s) static inline int has_bcr3_and_bcr4(SH7750State * s)
{ {
return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4); return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
} }
/********************************************************************** /**********************************************************************
I/O ports I/O ports
@ -271,21 +271,21 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
ignore_access("long read", addr); ignore_access("long read", addr);
return 0; return 0;
case SH7750_MMUCR_A7: case SH7750_MMUCR_A7:
return s->cpu->mmucr; return s->cpu->env.mmucr;
case SH7750_PTEH_A7: case SH7750_PTEH_A7:
return s->cpu->pteh; return s->cpu->env.pteh;
case SH7750_PTEL_A7: case SH7750_PTEL_A7:
return s->cpu->ptel; return s->cpu->env.ptel;
case SH7750_TTB_A7: case SH7750_TTB_A7:
return s->cpu->ttb; return s->cpu->env.ttb;
case SH7750_TEA_A7: case SH7750_TEA_A7:
return s->cpu->tea; return s->cpu->env.tea;
case SH7750_TRA_A7: case SH7750_TRA_A7:
return s->cpu->tra; return s->cpu->env.tra;
case SH7750_EXPEVT_A7: case SH7750_EXPEVT_A7:
return s->cpu->expevt; return s->cpu->env.expevt;
case SH7750_INTEVT_A7: case SH7750_INTEVT_A7:
return s->cpu->intevt; return s->cpu->env.intevt;
case SH7750_CCR_A7: case SH7750_CCR_A7:
return s->ccr; return s->ccr;
case 0x1f000030: /* Processor version */ case 0x1f000030: /* Processor version */
@ -409,36 +409,37 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
return; return;
case SH7750_MMUCR_A7: case SH7750_MMUCR_A7:
if (mem_value & MMUCR_TI) { if (mem_value & MMUCR_TI) {
cpu_sh4_invalidate_tlb(s->cpu); cpu_sh4_invalidate_tlb(&s->cpu->env);
} }
s->cpu->mmucr = mem_value & ~MMUCR_TI; s->cpu->env.mmucr = mem_value & ~MMUCR_TI;
return; return;
case SH7750_PTEH_A7: case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */ /* If asid changes, clear all registered tlb entries. */
if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
tlb_flush(s->cpu, 1); tlb_flush(&s->cpu->env, 1);
s->cpu->pteh = mem_value; }
s->cpu->env.pteh = mem_value;
return; return;
case SH7750_PTEL_A7: case SH7750_PTEL_A7:
s->cpu->ptel = mem_value; s->cpu->env.ptel = mem_value;
return; return;
case SH7750_PTEA_A7: case SH7750_PTEA_A7:
s->cpu->ptea = mem_value & 0x0000000f; s->cpu->env.ptea = mem_value & 0x0000000f;
return; return;
case SH7750_TTB_A7: case SH7750_TTB_A7:
s->cpu->ttb = mem_value; s->cpu->env.ttb = mem_value;
return; return;
case SH7750_TEA_A7: case SH7750_TEA_A7:
s->cpu->tea = mem_value; s->cpu->env.tea = mem_value;
return; return;
case SH7750_TRA_A7: case SH7750_TRA_A7:
s->cpu->tra = mem_value & 0x000007ff; s->cpu->env.tra = mem_value & 0x000007ff;
return; return;
case SH7750_EXPEVT_A7: case SH7750_EXPEVT_A7:
s->cpu->expevt = mem_value & 0x000007ff; s->cpu->env.expevt = mem_value & 0x000007ff;
return; return;
case SH7750_INTEVT_A7: case SH7750_INTEVT_A7:
s->cpu->intevt = mem_value & 0x000007ff; s->cpu->env.intevt = mem_value & 0x000007ff;
return; return;
case SH7750_CCR_A7: case SH7750_CCR_A7:
s->ccr = mem_value; s->ccr = mem_value;
@ -651,20 +652,20 @@ static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
/* do nothing */ /* do nothing */
break; break;
case MM_ITLB_ADDR: case MM_ITLB_ADDR:
ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
break; break;
case MM_ITLB_DATA: case MM_ITLB_DATA:
ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr);
break; break;
case MM_OCACHE_ADDR: case MM_OCACHE_ADDR:
case MM_OCACHE_DATA: case MM_OCACHE_DATA:
/* do nothing */ /* do nothing */
break; break;
case MM_UTLB_ADDR: case MM_UTLB_ADDR:
ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
break; break;
case MM_UTLB_DATA: case MM_UTLB_DATA:
ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr);
break; break;
default: default:
abort(); abort();
@ -694,10 +695,10 @@ static void sh7750_mmct_write(void *opaque, hwaddr addr,
/* do nothing */ /* do nothing */
break; break;
case MM_ITLB_ADDR: case MM_ITLB_ADDR:
cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
break; break;
case MM_ITLB_DATA: case MM_ITLB_DATA:
cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
abort(); abort();
break; break;
case MM_OCACHE_ADDR: case MM_OCACHE_ADDR:
@ -705,10 +706,10 @@ static void sh7750_mmct_write(void *opaque, hwaddr addr,
/* do nothing */ /* do nothing */
break; break;
case MM_UTLB_ADDR: case MM_UTLB_ADDR:
cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
break; break;
case MM_UTLB_DATA: case MM_UTLB_DATA:
cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
break; break;
default: default:
abort(); abort();
@ -722,7 +723,7 @@ static const MemoryRegionOps sh7750_mmct_ops = {
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
{ {
SH7750State *s; SH7750State *s;
@ -768,7 +769,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
_INTC_ARRAY(vectors), _INTC_ARRAY(vectors),
_INTC_ARRAY(groups)); _INTC_ARRAY(groups));
cpu->intc_handle = &s->intc; cpu->env.intc_handle = &s->intc;
sh_serial_init(sysmem, 0x1fe00000, sh_serial_init(sysmem, 0x1fe00000,
0, s->periph_freq, serial_hds[0], 0, s->periph_freq, serial_hds[0],
@ -794,19 +795,19 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
s->intc.irqs[TMU2_TUNI], s->intc.irqs[TMU2_TUNI],
s->intc.irqs[TMU2_TICPI]); s->intc.irqs[TMU2_TICPI]);
if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma4), _INTC_ARRAY(vectors_dma4),
_INTC_ARRAY(groups_dma4)); _INTC_ARRAY(groups_dma4));
} }
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma8), _INTC_ARRAY(vectors_dma8),
_INTC_ARRAY(groups_dma8)); _INTC_ARRAY(groups_dma8));
} }
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34), _INTC_ARRAY(vectors_tmu34),
NULL, 0); NULL, 0);
@ -816,13 +817,13 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
NULL, NULL); NULL, NULL);
} }
if (cpu->id & (SH_CPU_SH7751_ALL)) { if (cpu->env.id & (SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_pci), _INTC_ARRAY(vectors_pci),
_INTC_ARRAY(groups_pci)); _INTC_ARRAY(groups_pci));
} }
if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irlm), _INTC_ARRAY(vectors_irlm),
NULL, 0); NULL, 0);

8
hw/sh4/shix.c
View File

@ -41,7 +41,7 @@ static void shix_init(QEMUMachineInitArgs *args)
{ {
const char *cpu_model = args->cpu_model; const char *cpu_model = args->cpu_model;
int ret; int ret;
CPUSH4State *env; SuperHCPU *cpu;
struct SH7750State *s; struct SH7750State *s;
MemoryRegion *sysmem = get_system_memory(); MemoryRegion *sysmem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1); MemoryRegion *rom = g_new(MemoryRegion, 1);
@ -51,8 +51,8 @@ static void shix_init(QEMUMachineInitArgs *args)
cpu_model = "any"; cpu_model = "any";
printf("Initializing CPU\n"); printf("Initializing CPU\n");
env = cpu_init(cpu_model); cpu = cpu_sh4_init(cpu_model);
if (env == NULL) { if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n"); fprintf(stderr, "Unable to find CPU definition\n");
exit(1); exit(1);
} }
@ -85,7 +85,7 @@ static void shix_init(QEMUMachineInitArgs *args)
} }
/* Register peripherals */ /* Register peripherals */
s = sh7750_init(env, sysmem); s = sh7750_init(cpu, sysmem);
/* XXXXX Check success */ /* XXXXX Check success */
tc58128_init(s, "shix_linux_nand.bin", NULL); tc58128_init(s, "shix_linux_nand.bin", NULL);
fprintf(stderr, "initialization terminated\n"); fprintf(stderr, "initialization terminated\n");

2
include/hw/sh4/sh.h
View File

@ -11,7 +11,7 @@
struct SH7750State; struct SH7750State;
struct MemoryRegion; struct MemoryRegion;
struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion *sysmem); struct SH7750State *sh7750_init(SuperHCPU *cpu, struct MemoryRegion *sysmem);
typedef struct { typedef struct {
/* The callback will be triggered if any of the designated lines change */ /* The callback will be triggered if any of the designated lines change */