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MIPS queue for January 25, 2019 

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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-january-25-2019' into staging

MIPS queue for January 25, 2019

# gpg: Signature made Fri 25 Jan 2019 13:25:57 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-january-25-2019:
  docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models
  qemu-doc: Add nanoMIPS ISA information
  tests: tcg: mips: Remove old directories
  tests: tcg: mips: Add two new Makefiles
  tests: tcg: mips: Move source files to new locations
  MAINTAINERS: Update MIPS sections
  target/mips: Add I6500 core configuration
  target/mips: nanoMIPS: Fix branch handling
  disas: nanoMIPS: Amend DSP instructions related comments
  target/mips: Extend gen_scwp() functionality to support EVA
  target/mips: Correct the second argument type of cpu_supports_isa()
  target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers
  target/mips: nanoMIPS: Remove an unused macro
  target/mips: nanoMIPS: Remove duplicate macro definitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-01-25 16:31:02 +00:00
parent 9dd0d8111f e5a5b1bb7c
commit 2dc2f10de3
503 changed files with 531 additions and 13770 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
MAINTAINERS
View File

@ -206,7 +206,6 @@ MIPS
M: Aurelien Jarno <aurelien@aurel32.net>
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: target/mips/
F: default-configs/*mips*
@ -365,7 +364,6 @@ F: target/arm/kvm.c
MIPS
M: James Hogan <jhogan@kernel.org>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: target/mips/kvm.c
@ -890,7 +888,6 @@ MIPS Machines
Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/mips/mips_jazz.c
F: hw/display/jazz_led.c
@ -899,14 +896,12 @@ F: hw/dma/rc4030.c
Malta
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/mips/mips_malta.c
Mipssim
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
@ -914,14 +909,12 @@ F: hw/net/mipsnet.c
R4000
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/mips/mips_r4k.c
Fulong 2E
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
@ -931,7 +924,6 @@ F: include/hw/isa/vt82c686.h
Boston
M: Paul Burton <pburton@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
@ -2203,7 +2195,6 @@ F: disas/i386.c
MIPS target
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: tcg/mips/
F: disas/mips.c

119
disas/nanomips.cpp
View File

@ -1836,7 +1836,8 @@ std::string NMD::ABS_S(uint64 instruction)
/*
* ABSQ_S.PH rt, rs - Find Absolute Value of Two Fractional Halfwords
* [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
* with 16-bit saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -1857,7 +1858,8 @@ std::string NMD::ABSQ_S_PH(uint64 instruction)
/*
* ABSQ_S.QB rt, rs - Find Absolute Value of Four Fractional Byte Values
* [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
* with 8-bit saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -1878,7 +1880,8 @@ std::string NMD::ABSQ_S_QB(uint64 instruction)
/*
*
* [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
* saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -2233,7 +2236,7 @@ std::string NMD::ADDIUPC_48_(uint64 instruction)
/*
* ADDQ.PH rd, rt, rs - Add Fractional Halfword Vectors
* [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
*
* 3 2 1
* 10987654321098765432109876543210
@ -2257,7 +2260,8 @@ std::string NMD::ADDQ_PH(uint64 instruction)
/*
* ADDQ_S.PH rd, rt, rs - Add Fractional Halfword Vectors
* [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
* saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -2281,7 +2285,7 @@ std::string NMD::ADDQ_S_PH(uint64 instruction)
/*
* ADDQ_S.W rd, rt, rs - Add Fractional Words
* [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -2305,8 +2309,8 @@ std::string NMD::ADDQ_S_W(uint64 instruction)
/*
* ADDQH.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
* to Halve Results
* [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
* right to halve results
*
* 3 2 1
* 10987654321098765432109876543210
@ -2330,8 +2334,8 @@ std::string NMD::ADDQH_PH(uint64 instruction)
/*
* ADDQH_R.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
* to Halve Results
* [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
* right to halve results with rounding
*
* 3 2 1
* 10987654321098765432109876543210
@ -2355,7 +2359,8 @@ std::string NMD::ADDQH_R_PH(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
* results with rounding
*
* 3 2 1
* 10987654321098765432109876543210
@ -2379,7 +2384,8 @@ std::string NMD::ADDQH_R_W(uint64 instruction)
/*
* ADDQH.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
* results
*
* 3 2 1
* 10987654321098765432109876543210
@ -2403,7 +2409,7 @@ std::string NMD::ADDQH_W(uint64 instruction)
/*
* ADDSC rd, rt, rs - Add Signed Word and Set Carry Bit
* [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
*
* 3 2 1
* 10987654321098765432109876543210
@ -2496,7 +2502,7 @@ std::string NMD::ADDU_4X4_(uint64 instruction)
/*
* ADDU.PH rd, rt, rs - Unsigned Add Integer Halfwords
* [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
*
* 3 2 1
* 10987654321098765432109876543210
@ -2544,7 +2550,8 @@ std::string NMD::ADDU_QB(uint64 instruction)
/*
* ADDU_S.PH rd, rt, rs - Unsigned Add Integer Halfwords
* [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
* saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -7848,7 +7855,7 @@ std::string NMD::INS(uint64 instruction)
/*
*
* [DSP] INSV - Insert bit field variable
*
* 3 2 1
* 10987654321098765432109876543210
@ -9698,7 +9705,8 @@ std::string NMD::LWXS_32_(uint64 instruction)
/*
*
* [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
* accumulator
*
* 3 2 1
* 10987654321098765432109876543210
@ -9770,7 +9778,8 @@ std::string NMD::MADDF_S(uint64 instruction)
/*
*
* [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
* specified accumulator
*
* 3 2 1
* 10987654321098765432109876543210
@ -9794,7 +9803,8 @@ std::string NMD::MADDU_DSP_(uint64 instruction)
/*
*
* [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
* fractional halfword elements with accumulation
*
* 3 2 1
* 10987654321098765432109876543210
@ -9818,7 +9828,8 @@ std::string NMD::MAQ_S_W_PHL(uint64 instruction)
/*
*
* [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
* fractional halfword elements with accumulation
*
* 3 2 1
* 10987654321098765432109876543210
@ -9842,7 +9853,8 @@ std::string NMD::MAQ_S_W_PHR(uint64 instruction)
/*
*
* [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
* fractional halfword elements with saturating accumulation
*
* 3 2 1
* 10987654321098765432109876543210
@ -9866,7 +9878,8 @@ std::string NMD::MAQ_SA_W_PHL(uint64 instruction)
/*
*
* [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
* fractional halfword elements with saturating accumulation
*
* 3 2 1
* 10987654321098765432109876543210
@ -11722,7 +11735,8 @@ std::string NMD::ORI(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
* source register and left halfword from another source register
*
* 3 2 1
* 10987654321098765432109876543210
@ -11764,7 +11778,8 @@ std::string NMD::PAUSE(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
* code bits
*
* 3 2 1
* 10987654321098765432109876543210
@ -11788,7 +11803,8 @@ std::string NMD::PICK_PH(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
* code bits
*
* 3 2 1
* 10987654321098765432109876543210
@ -11812,7 +11828,8 @@ std::string NMD::PICK_QB(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
* of a paired halfword
*
* 3 2 1
* 10987654321098765432109876543210
@ -11834,7 +11851,8 @@ std::string NMD::PRECEQ_W_PHL(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
* of a paired halfword
*
* 3 2 1
* 10987654321098765432109876543210
@ -11856,7 +11874,8 @@ std::string NMD::PRECEQ_W_PHR(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
* left-alternate elements of a quad byte vector
*
* 3 2 1
* 10987654321098765432109876543210
@ -11878,7 +11897,8 @@ std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
* elements of a quad byte vector
*
* 3 2 1
* 10987654321098765432109876543210
@ -11900,7 +11920,8 @@ std::string NMD::PRECEQU_PH_QBL(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
* right-alternate elements of a quad byte vector
*
* 3 2 1
* 10987654321098765432109876543210
@ -11922,7 +11943,8 @@ std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
* elements of a quad byte vector
*
* 3 2 1
* 10987654321098765432109876543210
@ -11944,7 +11966,9 @@ std::string NMD::PRECEQU_PH_QBR(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
* left-alternate elements of a quad byte vector to four unsigned
* halfwords
*
* 3 2 1
* 10987654321098765432109876543210
@ -11966,7 +11990,8 @@ std::string NMD::PRECEU_PH_QBLA(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
* elements of a quad byte vector to form unsigned halfwords
*
* 3 2 1
* 10987654321098765432109876543210
@ -11988,7 +12013,9 @@ std::string NMD::PRECEU_PH_QBL(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
* right-alternate elements of a quad byte vector to form four
* unsigned halfwords
*
* 3 2 1
* 10987654321098765432109876543210
@ -12010,7 +12037,8 @@ std::string NMD::PRECEU_PH_QBRA(uint64 instruction)
/*
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
* [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
* elements of a quad byte vector to form unsigned halfwords
*
* 3 2 1
* 10987654321098765432109876543210
@ -15202,7 +15230,7 @@ std::string NMD::SUBU_32_(uint64 instruction)
/*
* SUBU.PH rd, rs, rt - Subtract Unsigned Integer Halfwords
* [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
*
* 3 2 1
* 10987654321098765432109876543210
@ -15226,7 +15254,7 @@ std::string NMD::SUBU_PH(uint64 instruction)
/*
* SUBU.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector
* [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
*
* 3 2 1
* 10987654321098765432109876543210
@ -15250,7 +15278,8 @@ std::string NMD::SUBU_QB(uint64 instruction)
/*
* SUBU_S.PH rd, rs, rt - Subtract Unsigned Integer Halfwords (saturating)
* [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
* 8-bit saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -15274,7 +15303,8 @@ std::string NMD::SUBU_S_PH(uint64 instruction)
/*
* SUBU_S.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector (saturating)
* [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
* 8-bit saturation
*
* 3 2 1
* 10987654321098765432109876543210
@ -15298,8 +15328,8 @@ std::string NMD::SUBU_S_QB(uint64 instruction)
/*
* SUBUH.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
* Results
* [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
* to halve results
*
* 3 2 1
* 10987654321098765432109876543210
@ -15323,8 +15353,8 @@ std::string NMD::SUBUH_QB(uint64 instruction)
/*
* SUBUH_R.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
* Results (rounding)
* [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
* to halve results with rounding
*
* 3 2 1
* 10987654321098765432109876543210
@ -16412,7 +16442,8 @@ std::string NMD::WAIT(uint64 instruction)
/*
* WRDSP rt, mask - Write Fields to DSPControl Register from a GPR
* [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
* register
*
* 3 2 1
* 10987654321098765432109876543210

163
docs/qemu-cpu-models.texi
View File

@ -5,8 +5,9 @@ QEMU / KVM CPU model configuration
@c man begin DESCRIPTION
@menu
* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
* cpu_model_syntax_apps:: Syntax for configuring CPU models
* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
* recommendations_cpu_models_MIPS:: Supported CPU model configurations on MIPS hosts
* cpu_model_syntax_apps:: Syntax for configuring CPU models
@end menu
QEMU / KVM virtualization supports two ways to configure CPU models
@ -368,6 +369,164 @@ hardware assisted virtualization, that should thus not be required for
running virtual machines.
@end table
@node recommendations_cpu_models_MIPS
@subsection Supported CPU model configurations on MIPS hosts
QEMU supports variety of MIPS CPU models:
@menu
* cpu_models_MIPS32:: Supported CPU models for MIPS32 hosts
* cpu_models_MIPS64:: Supported CPU models for MIPS64 hosts
* cpu_models_nanoMIPS:: Supported CPU models for nanoMIPS hosts
* preferred_cpu_models_MIPS:: Preferred CPU models for MIPS hosts
@end menu
@node cpu_models_MIPS32
@subsubsection Supported CPU models for MIPS32 hosts
The following CPU models are supported for use on MIPS32 hosts. Administrators /
applications are recommended to use the CPU model that matches the generation
of the host CPUs in use. In a deployment with a mixture of host CPU models
between machines, if live migration compatibility is required, use the newest
CPU model that is compatible across all desired hosts.
@table @option
@item @code{mips32r6-generic}
MIPS32 Processor (Release 6, 2015)
@item @code{P5600}
MIPS32 Processor (P5600, 2014)
@item @code{M14K}
@item @code{M14Kc}
MIPS32 Processor (M14K, 2009)
@item @code{74Kf}
MIPS32 Processor (74K, 2007)
@item @code{34Kf}
MIPS32 Processor (34K, 2006)
@item @code{24Kc}
@item @code{24KEc}
@item @code{24Kf}
MIPS32 Processor (24K, 2003)
@item @code{4Kc}
@item @code{4Km}
@item @code{4KEcR1}
@item @code{4KEmR1}
@item @code{4KEc}
@item @code{4KEm}
MIPS32 Processor (4K, 1999)
@end table
@node cpu_models_MIPS64
@subsubsection Supported CPU models for MIPS64 hosts
The following CPU models are supported for use on MIPS64 hosts. Administrators /
applications are recommended to use the CPU model that matches the generation
of the host CPUs in use. In a deployment with a mixture of host CPU models
between machines, if live migration compatibility is required, use the newest
CPU model that is compatible across all desired hosts.
@table @option
@item @code{I6400}
MIPS64 Processor (Release 6, 2014)
@item @code{Loongson-2F}
MIPS64 Processor (Longsoon 2, 2008)
@item @code{Loongson-2E}
MIPS64 Processor (Loongson 2, 2006)
@item @code{mips64dspr2}
MIPS64 Processor (Release 2, 2006)
@item @code{MIPS64R2-generic}
@item @code{5KEc}
@item @code{5KEf}
MIPS64 Processor (Release 2, 2002)
@item @code{20Kc}
MIPS64 Processor (20K, 2000)
@item @code{5Kc}
@item @code{5Kf}
MIPS64 Processor (5K, 1999)
@item @code{VR5432}
MIPS64 Processor (VR, 1998)
@item @code{R4000}
MIPS64 Processor (MIPS III, 1991)
@end table
@node cpu_models_nanoMIPS
@subsubsection Supported CPU models for nanoMIPS hosts
The following CPU models are supported for use on nanoMIPS hosts. Administrators /
applications are recommended to use the CPU model that matches the generation
of the host CPUs in use. In a deployment with a mixture of host CPU models
between machines, if live migration compatibility is required, use the newest
CPU model that is compatible across all desired hosts.
@table @option
@item @code{I7200}
MIPS I7200 (nanoMIPS, 2018)
@end table
@node preferred_cpu_models_MIPS
@subsubsection Preferred CPU models for MIPS hosts
The following CPU models are preferred for use on different MIPS hosts:
@table @option
@item @code{MIPS III}
R4000
@item @code{MIPS32R2}
34Kf
@item @code{MIPS64R6}
I6400
@item @code{nanoMIPS}
I7200
@end table
@node cpu_model_syntax_apps
@subsection Syntax for configuring CPU models

29
qemu-doc.texi
View File

@ -1995,6 +1995,10 @@ Set the emulated machine type. The default is sun4u.
@section MIPS System emulator
@cindex system emulation (MIPS)
@menu
* nanoMIPS System emulator ::
@end menu
Four executables cover simulation of 32 and 64-bit MIPS systems in
both endian options, @file{qemu-system-mips}, @file{qemu-system-mipsel}
@file{qemu-system-mips64} and @file{qemu-system-mips64el}.
@ -2086,6 +2090,31 @@ SCSI controller
G364 framebuffer
@end itemize
@node nanoMIPS System emulator
@subsection nanoMIPS System emulator
@cindex system emulation (nanoMIPS)
Executable @file{qemu-system-mipsel} also covers simulation of
32-bit nanoMIPS system in little endian mode:
@itemize @minus
@item
nanoMIPS I7200 CPU
@end itemize
Example of @file{qemu-system-mipsel} usage for nanoMIPS is shown below:
Download @code{<disk_image_file>} from @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/buildroot/index.html}.
Download @code{<kernel_image_file>} from @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/index.html}.
Start system emulation of Malta board with nanoMIPS I7200 CPU:
@example
qemu-system-mipsel -cpu I7200 -kernel @code{<kernel_image_file>} \
-M malta -serial stdio -m @code{<memory_size>} -hda @code{<disk_image_file>} \
-append "mem=256m@@0x0 rw console=ttyS0 vga=cirrus vesa=0x111 root=/dev/sda"
@end example
@node ARM System emulator
@section ARM System emulator

2
target/mips/cpu.h
View File

@ -1173,7 +1173,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
bool cpu_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
/* mips_int.c */

61
target/mips/translate.c
View File

@ -3714,7 +3714,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
}
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
uint32_t reg1, uint32_t reg2)
uint32_t reg1, uint32_t reg2, bool eva)
{
TCGv taddr = tcg_temp_local_new();
TCGv lladdr = tcg_temp_local_new();
@ -3742,7 +3742,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
ctx->mem_idx, MO_64);
eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
if (reg1 != 0) {
tcg_gen_movi_tl(cpu_gpr[reg1], 1);
}
@ -18460,10 +18460,9 @@ enum {
/* extraction utilities */
#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
@ -18502,16 +18501,6 @@ static inline int decode_gpr_gpr4_zero(int r)
}
/* extraction utilities */
#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
static void gen_adjust_sp(DisasContext *ctx, int u)
{
gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u);
@ -18570,8 +18559,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
{
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
switch (extract32(ctx->opcode, 2, 2)) {
case NM_NOT16:
@ -19769,6 +19758,10 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
goto out;
}
/* branch completion */
clear_branch_hflags(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
if (bcond_compute == 0) {
/* Uncoditional compact branch */
gen_goto_tb(ctx, 0, ctx->btarget);
@ -19809,6 +19802,10 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
gen_op_addr_add(ctx, btarget, t1, t0);
/* branch completion */
clear_branch_hflags(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
/* unconditional branch to register */
tcg_gen_mov_tl(cpu_PC, btarget);
tcg_gen_lookup_and_goto_ptr();
@ -19947,6 +19944,10 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
goto out;
}
/* branch completion */
clear_branch_hflags(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
/* Generating branch here as compact branches don't have delay slot */
gen_goto_tb(ctx, 1, ctx->btarget);
gen_set_label(fs);
@ -21561,7 +21562,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SCWP:
check_xnp(ctx);
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
false);
break;
}
break;
@ -21665,7 +21667,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
true);
break;
default:
generate_exception_end(ctx, EXCP_RI);
@ -21872,9 +21875,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
int offset;
int imm;
@ -22037,7 +22040,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SB16:
rt = decode_gpr_gpr3_src_store(
NANOMIPS_EXTRACT_RD(ctx->opcode));
NANOMIPS_EXTRACT_RT3(ctx->opcode));
gen_st(ctx, OPC_SB, rt, rs, offset);
break;
case NM_LBU16:
@ -22056,7 +22059,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SH16:
rt = decode_gpr_gpr3_src_store(
NANOMIPS_EXTRACT_RD(ctx->opcode));
NANOMIPS_EXTRACT_RT3(ctx->opcode));
gen_st(ctx, OPC_SH, rt, rs, offset);
break;
case NM_LHU16:
@ -22111,14 +22114,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SW16:
rt = decode_gpr_gpr3_src_store(
NANOMIPS_EXTRACT_RD(ctx->opcode));
rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
NANOMIPS_EXTRACT_RT3(ctx->opcode));
rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
offset = extract32(ctx->opcode, 0, 4) << 2;
gen_st(ctx, OPC_SW, rt, rs, offset);
break;
case NM_SWGP16:
rt = decode_gpr_gpr3_src_store(
NANOMIPS_EXTRACT_RD(ctx->opcode));
NANOMIPS_EXTRACT_RT3(ctx->opcode));
offset = extract32(ctx->opcode, 0, 7) << 2;
gen_st(ctx, OPC_SW, rt, 28, offset);
break;
@ -29894,7 +29897,7 @@ bool cpu_supports_cps_smp(const char *cpu_type)
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
{
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->insn_flags & isa) != 0;

40
target/mips/translate_init.inc.c
View File

@ -721,6 +721,46 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS64R6 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "I6500",
.CP0_PRid = 0x1B000,
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
(MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
(2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
(2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
(1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 64,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x30D8FFFF,
.CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
(1U << CP0PG_RIE),
.CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
.CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.CP1_fcr31_rw_bitmask = 0x0103FFFF,
.MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_MIPS64R6 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "Loongson-2E",
.CP0_PRid = 0x6302,

136
tests/tcg/mips/mips32-dsp/Makefile
View File

@ -1,136 +0,0 @@
-include ../../config-host.mak
CROSS=mips64el-unknown-linux-gnu-
SIM=qemu-mipsel
SIM_FLAGS=-cpu 74Kf
CC = $(CROSS)gcc
CFLAGS = -mabi=32 -march=mips32r2 -mgp32 -mdsp -static
TESTCASES = absq_s_ph.tst
TESTCASES += absq_s_w.tst
TESTCASES += addq_ph.tst
TESTCASES += addq_s_ph.tst
TESTCASES += addq_s_w.tst
TESTCASES += addsc.tst
TESTCASES += addu_qb.tst
TESTCASES += addu_s_qb.tst
TESTCASES += addwc.tst
TESTCASES += bitrev.tst
TESTCASES += bposge32.tst
TESTCASES += cmp_eq_ph.tst
TESTCASES += cmpgu_eq_qb.tst
TESTCASES += cmpgu_le_qb.tst
TESTCASES += cmpgu_lt_qb.tst
TESTCASES += cmp_le_ph.tst
TESTCASES += cmp_lt_ph.tst
TESTCASES += cmpu_eq_qb.tst
TESTCASES += cmpu_le_qb.tst
TESTCASES += cmpu_lt_qb.tst
TESTCASES += dpaq_sa_l_w.tst
TESTCASES += dpaq_s_w_ph.tst
TESTCASES += dpau_h_qbl.tst
TESTCASES += dpau_h_qbr.tst
TESTCASES += dpsq_sa_l_w.tst
TESTCASES += dpsq_s_w_ph.tst
TESTCASES += dpsu_h_qbl.tst
TESTCASES += dpsu_h_qbr.tst
TESTCASES += extp.tst
TESTCASES += extpdp.tst
TESTCASES += extpdpv.tst
TESTCASES += extpv.tst
TESTCASES += extr_rs_w.tst
TESTCASES += extr_r_w.tst
TESTCASES += extr_s_h.tst
TESTCASES += extrv_rs_w.tst
TESTCASES += extrv_r_w.tst
TESTCASES += extrv_s_h.tst
TESTCASES += extrv_w.tst
TESTCASES += extr_w.tst
TESTCASES += insv.tst
TESTCASES += lbux.tst
TESTCASES += lhx.tst
TESTCASES += lwx.tst
TESTCASES += madd.tst
TESTCASES += maddu.tst
TESTCASES += maq_sa_w_phl.tst
TESTCASES += maq_sa_w_phr.tst
TESTCASES += maq_s_w_phl.tst
TESTCASES += maq_s_w_phr.tst
TESTCASES += mfhi.tst
TESTCASES += mflo.tst
TESTCASES += modsub.tst
TESTCASES += msub.tst
TESTCASES += msubu.tst
TESTCASES += mthi.tst
TESTCASES += mthlip.tst
TESTCASES += mtlo.tst
TESTCASES += muleq_s_w_phl.tst
TESTCASES += muleq_s_w_phr.tst
TESTCASES += muleu_s_ph_qbl.tst
TESTCASES += muleu_s_ph_qbr.tst
TESTCASES += mulq_rs_ph.tst
TESTCASES += mult.tst
TESTCASES += multu.tst
TESTCASES += packrl_ph.tst
TESTCASES += pick_ph.tst
TESTCASES += pick_qb.tst
TESTCASES += precequ_ph_qbla.tst
TESTCASES += precequ_ph_qbl.tst
TESTCASES += precequ_ph_qbra.tst
TESTCASES += precequ_ph_qbr.tst
TESTCASES += preceq_w_phl.tst
TESTCASES += preceq_w_phr.tst
TESTCASES += preceu_ph_qbla.tst
TESTCASES += preceu_ph_qbl.tst
TESTCASES += preceu_ph_qbra.tst
TESTCASES += preceu_ph_qbr.tst
TESTCASES += precrq_ph_w.tst
TESTCASES += precrq_qb_ph.tst
TESTCASES += precrq_rs_ph_w.tst
TESTCASES += precrqu_s_qb_ph.tst
TESTCASES += raddu_w_qb.tst
TESTCASES += rddsp.tst
TESTCASES += repl_ph.tst
TESTCASES += repl_qb.tst
TESTCASES += replv_ph.tst
TESTCASES += replv_qb.tst
TESTCASES += shilo.tst
TESTCASES += shilov.tst
TESTCASES += shll_ph.tst
TESTCASES += shll_qb.tst
TESTCASES += shll_s_ph.tst
TESTCASES += shll_s_w.tst
TESTCASES += shllv_ph.tst
TESTCASES += shllv_qb.tst
TESTCASES += shllv_s_ph.tst
TESTCASES += shllv_s_w.tst
TESTCASES += shra_ph.tst
TESTCASES += shra_r_ph.tst
TESTCASES += shra_r_w.tst
TESTCASES += shrav_ph.tst
TESTCASES += shrav_r_ph.tst
TESTCASES += shrav_r_w.tst
TESTCASES += shrl_qb.tst
TESTCASES += shrlv_qb.tst
TESTCASES += subq_ph.tst
TESTCASES += subq_s_ph.tst
TESTCASES += subq_s_w.tst
TESTCASES += subu_qb.tst
TESTCASES += subu_s_qb.tst
TESTCASES += wrdsp.tst
all: $(TESTCASES)
%.tst: %.c
$(CC) $(CFLAGS) $< -o $@
check: $(TESTCASES)
@for case in $(TESTCASES); do \
echo $(SIM) $(SIM_FLAGS) ./$$case;\
$(SIM) $(SIM_FLAGS) ./$$case; \
done
clean:
$(RM) -rf $(TESTCASES)

71
tests/tcg/mips/mips32-dspr2/Makefile
View File

@ -1,71 +0,0 @@
-include ../../config-host.mak
CROSS=mips64el-unknown-linux-gnu-
SIM=qemu-mipsel
SIM_FLAGS=-cpu 74Kf
CC = $(CROSS)gcc
CFLAGS = -mabi=32 -march=mips32r2 -mgp32 -mdspr2 -static
TESTCASES = absq_s_qb.tst
TESTCASES += addqh_ph.tst
TESTCASES += addqh_r_ph.tst
TESTCASES += addqh_r_w.tst
TESTCASES += addqh_w.tst
TESTCASES += adduh_qb.tst
TESTCASES += adduh_r_qb.tst
TESTCASES += addu_ph.tst
TESTCASES += addu_s_ph.tst
TESTCASES += append.tst
TESTCASES += balign.tst
TESTCASES += cmpgdu_eq_qb.tst
TESTCASES += cmpgdu_le_qb.tst
TESTCASES += cmpgdu_lt_qb.tst
TESTCASES += dpaqx_sa_w_ph.tst
TESTCASES += dpa_w_ph.tst
TESTCASES += dpax_w_ph.tst
TESTCASES += dpaqx_s_w_ph.tst
TESTCASES += dpsqx_sa_w_ph.tst
TESTCASES += dpsqx_s_w_ph.tst
TESTCASES += dps_w_ph.tst
TESTCASES += dpsx_w_ph.tst
TESTCASES += mul_ph.tst
TESTCASES += mulq_rs_w.tst
TESTCASES += mulq_s_ph.tst
TESTCASES += mulq_s_w.tst
TESTCASES += mulsaq_s_w_ph.tst
TESTCASES += mulsa_w_ph.tst
TESTCASES += mul_s_ph.tst
TESTCASES += precr_qb_ph.tst
TESTCASES += precr_sra_ph_w.tst
TESTCASES += precr_sra_r_ph_w.tst
TESTCASES += prepend.tst
TESTCASES += shra_qb.tst
TESTCASES += shra_r_qb.tst
TESTCASES += shrav_qb.tst
TESTCASES += shrav_r_qb.tst
TESTCASES += shrl_ph.tst
TESTCASES += shrlv_ph.tst
TESTCASES += subqh_ph.tst
TESTCASES += subqh_r_ph.tst
TESTCASES += subqh_r_w.tst
TESTCASES += subqh_w.tst
TESTCASES += subuh_qb.tst
TESTCASES += subuh_r_qb.tst
TESTCASES += subu_ph.tst
TESTCASES += subu_s_ph.tst
all: $(TESTCASES)
%.tst: %.c
$(CC) $(CFLAGS) $< -o $@
check: $(TESTCASES)
@for case in $(TESTCASES); do \
echo $(SIM) $(SIM_FLAGS) ./$$case;\
$(SIM) $(SIM_FLAGS) ./$$case; \
done
clean:
$(RM) -rf $(TESTCASES)

306
tests/tcg/mips/mips64-dsp/Makefile
View File

@ -1,306 +0,0 @@
CROSS_COMPILE ?= mips64el-unknown-linux-gnu-
SIM = qemu-system-mips64el
SIMFLAGS = -nographic -cpu mips64dspr2 -kernel
AS = $(CROSS_COMPILE)as
LD = $(CROSS_COMPILE)ld
CC = $(CROSS_COMPILE)gcc
AR = $(CROSS_COMPILE)ar
NM = $(CROSS_COMPILE)nm
STRIP = $(CROSS_COMPILE)strip
RANLIB = $(CROSS_COMPILE)ranlib
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
VECTORS_OBJ ?= ./head.o ./printf.o
HEAD_FLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -pipe \
-msoft-float -march=mips64 -Wa,-mips64 -Wa,--trap \
-msym32 -DKBUILD_64BIT_SYM32 -I./
CFLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -fno-builtin \
-pipe -march=mips64r2 -mgp64 -mdsp -static -Wa,--trap -msym32 \
-DKBUILD_64BIT_SYM32 -I./
LDFLAGS = -T./mips_boot.lds -L./
FLAGS = -nostdlib -mabi=64 -march=mips64r2 -mgp64 -mdsp
#TESTCASES = absq_s_ob.tst
TESTCASES = absq_s_ph.tst
TESTCASES += absq_s_pw.tst
TESTCASES += absq_s_qh.tst
TESTCASES += absq_s_w.tst
TESTCASES += addq_ph.tst
TESTCASES += addq_pw.tst
TESTCASES += addq_qh.tst
TESTCASES += addq_s_ph.tst
TESTCASES += addq_s_pw.tst
TESTCASES += addq_s_qh.tst
TESTCASES += addq_s_w.tst
TESTCASES += addsc.tst
TESTCASES += addu_ob.tst
TESTCASES += addu_qb.tst
TESTCASES += addu_s_ob.tst
TESTCASES += addu_s_qb.tst
TESTCASES += addwc.tst
TESTCASES += bitrev.tst
TESTCASES += bposge32.tst
TESTCASES += bposge64.tst
TESTCASES += cmp_eq_ph.tst
TESTCASES += cmp_eq_pw.tst
TESTCASES += cmp_eq_qh.tst
TESTCASES += cmpgu_eq_ob.tst
TESTCASES += cmpgu_eq_qb.tst
TESTCASES += cmpgu_le_ob.tst
TESTCASES += cmpgu_le_qb.tst
TESTCASES += cmpgu_lt_ob.tst
TESTCASES += cmpgu_lt_qb.tst
TESTCASES += cmp_le_ph.tst
TESTCASES += cmp_le_pw.tst
TESTCASES += cmp_le_qh.tst
TESTCASES += cmp_lt_ph.tst
TESTCASES += cmp_lt_pw.tst
TESTCASES += cmp_lt_qh.tst
TESTCASES += cmpu_eq_ob.tst
TESTCASES += cmpu_eq_qb.tst
TESTCASES += cmpu_le_ob.tst
TESTCASES += cmpu_le_qb.tst
TESTCASES += cmpu_lt_ob.tst
TESTCASES += cmpu_lt_qb.tst
#TESTCASES += dappend.tst
TESTCASES += dextp.tst
TESTCASES += dextpdp.tst
TESTCASES += dextpdpv.tst
TESTCASES += dextpv.tst
TESTCASES += dextr_l.tst
TESTCASES += dextr_r_l.tst
TESTCASES += dextr_rs_l.tst
TESTCASES += dextr_rs_w.tst
TESTCASES += dextr_r_w.tst
TESTCASES += dextr_s_h.tst
TESTCASES += dextrv_l.tst
TESTCASES += dextrv_r_l.tst
TESTCASES += dextrv_rs_l.tst
TESTCASES += dextrv_rs_w.tst
TESTCASES += dextrv_r_w.tst
TESTCASES += dextrv_s_h.tst
TESTCASES += dextrv_w.tst
TESTCASES += dextr_w.tst
TESTCASES += dinsv.tst
TESTCASES += dmadd.tst
TESTCASES += dmaddu.tst
TESTCASES += dmsub.tst
TESTCASES += dmsubu.tst
TESTCASES += dmthlip.tst
TESTCASES += dpaq_sa_l_pw.tst
TESTCASES += dpaq_sa_l_w.tst
TESTCASES += dpaq_s_w_ph.tst
TESTCASES += dpaq_s_w_qh.tst
TESTCASES += dpau_h_obl.tst
TESTCASES += dpau_h_obr.tst
TESTCASES += dpau_h_qbl.tst
TESTCASES += dpau_h_qbr.tst
TESTCASES += dpsq_sa_l_pw.tst
TESTCASES += dpsq_sa_l_w.tst
TESTCASES += dpsq_s_w_ph.tst
TESTCASES += dpsq_s_w_qh.tst
TESTCASES += dpsu_h_obl.tst
TESTCASES += dpsu_h_obr.tst
TESTCASES += dpsu_h_qbl.tst
TESTCASES += dpsu_h_qbr.tst
TESTCASES += dshilo.tst
TESTCASES += dshilov.tst
TESTCASES += extp.tst
TESTCASES += extpdp.tst
TESTCASES += extpdpv.tst
TESTCASES += extpv.tst
TESTCASES += extr_rs_w.tst
TESTCASES += extr_r_w.tst
TESTCASES += extr_s_h.tst
TESTCASES += extrv_rs_w.tst
TESTCASES += extrv_r_w.tst
TESTCASES += extrv_s_h.tst
TESTCASES += extrv_w.tst
TESTCASES += extr_w.tst
TESTCASES += insv.tst
TESTCASES += lbux.tst
TESTCASES += lhx.tst
TESTCASES += lwx.tst
TESTCASES += ldx.tst
TESTCASES += madd.tst
TESTCASES += maddu.tst
TESTCASES += maq_sa_w_phl.tst
TESTCASES += maq_sa_w_phr.tst
TESTCASES += maq_sa_w_qhll.tst
TESTCASES += maq_sa_w_qhlr.tst
TESTCASES += maq_sa_w_qhrl.tst
TESTCASES += maq_sa_w_qhrr.tst
TESTCASES += maq_s_l_pwl.tst
TESTCASES += maq_s_l_pwr.tst
TESTCASES += maq_s_w_phl.tst
TESTCASES += maq_s_w_phr.tst
TESTCASES += maq_s_w_qhll.tst
TESTCASES += maq_s_w_qhlr.tst
TESTCASES += maq_s_w_qhrl.tst
TESTCASES += maq_s_w_qhrr.tst
TESTCASES += mfhi.tst
TESTCASES += mflo.tst
TESTCASES += modsub.tst
TESTCASES += msub.tst
TESTCASES += msubu.tst
TESTCASES += mthi.tst
TESTCASES += mthlip.tst
TESTCASES += mtlo.tst
TESTCASES += muleq_s_pw_qhl.tst
TESTCASES += muleq_s_pw_qhr.tst
TESTCASES += muleq_s_w_phl.tst
TESTCASES += muleq_s_w_phr.tst
TESTCASES += muleu_s_ph_qbl.tst
TESTCASES += muleu_s_ph_qbr.tst
TESTCASES += muleu_s_qh_obl.tst
TESTCASES += muleu_s_qh_obr.tst
TESTCASES += mulq_rs_ph.tst
TESTCASES += mulq_rs_qh.tst
TESTCASES += mulsaq_s_l_pw.tst
TESTCASES += mulsaq_s_w_qh.tst
TESTCASES += mult.tst
TESTCASES += multu.tst
TESTCASES += packrl_ph.tst
TESTCASES += packrl_pw.tst
TESTCASES += pick_ob.tst
TESTCASES += pick_ph.tst
TESTCASES += pick_pw.tst
TESTCASES += pick_qb.tst
TESTCASES += pick_qh.tst
#TESTCASES += preceq_l_pwl.tst
#TESTCASES += preceq_l_pwr.tst
TESTCASES += preceq_pw_qhla.tst
TESTCASES += preceq_pw_qhl.tst
TESTCASES += preceq_pw_qhra.tst
TESTCASES += preceq_pw_qhr.tst
TESTCASES += precequ_ph_qbla.tst
TESTCASES += precequ_ph_qbl.tst
TESTCASES += precequ_ph_qbra.tst
TESTCASES += precequ_ph_qbr.tst
#TESTCASES += precequ_qh_obla.tst
#TESTCASES += precequ_qh_obl.tst
#TESTCASES += precequ_qh_obra.tst
#TESTCASES += precequ_qh_obr.tst
TESTCASES += preceq_w_phl.tst
TESTCASES += preceq_w_phr.tst
TESTCASES += preceu_ph_qbla.tst
TESTCASES += preceu_ph_qbl.tst
TESTCASES += preceu_ph_qbra.tst
TESTCASES += preceu_ph_qbr.tst
TESTCASES += preceu_qh_obla.tst
TESTCASES += preceu_qh_obl.tst
TESTCASES += preceu_qh_obra.tst
TESTCASES += preceu_qh_obr.tst
#TESTCASES += precr_ob_qh.tst
TESTCASES += precrq_ob_qh.tst
TESTCASES += precrq_ph_w.tst
TESTCASES += precrq_pw_l.tst
TESTCASES += precrq_qb_ph.tst
TESTCASES += precrq_qh_pw.tst
TESTCASES += precrq_rs_ph_w.tst
TESTCASES += precrq_rs_qh_pw.tst
TESTCASES += precrqu_s_ob_qh.tst
TESTCASES += precrqu_s_qb_ph.tst
#TESTCASES += precr_sra_qh_pw.tst
#TESTCASES += precr_sra_r_qh_pw.tst
#TESTCASES += prependd.tst
#TESTCASES += prependw.tst
#TESTCASES += raddu_l_ob.tst
TESTCASES += raddu_w_qb.tst
TESTCASES += rddsp.tst
TESTCASES += repl_ob.tst
TESTCASES += repl_ph.tst
TESTCASES += repl_pw.tst
TESTCASES += repl_qb.tst
TESTCASES += repl_qh.tst
TESTCASES += replv_ob.tst
TESTCASES += replv_ph.tst
TESTCASES += replv_pw.tst
TESTCASES += replv_qb.tst
TESTCASES += shilo.tst
TESTCASES += shilov.tst
TESTCASES += shll_ob.tst
TESTCASES += shll_ph.tst
TESTCASES += shll_pw.tst
TESTCASES += shll_qb.tst
TESTCASES += shll_qh.tst
TESTCASES += shll_s_ph.tst
TESTCASES += shll_s_pw.tst
TESTCASES += shll_s_qh.tst
TESTCASES += shll_s_w.tst
TESTCASES += shllv_ob.tst
TESTCASES += shllv_ph.tst
TESTCASES += shllv_pw.tst
TESTCASES += shllv_qb.tst
TESTCASES += shllv_qh.tst
TESTCASES += shllv_s_ph.tst
TESTCASES += shllv_s_pw.tst
TESTCASES += shllv_s_qh.tst
TESTCASES += shllv_s_w.tst
#TESTCASES += shra_ob.tst
TESTCASES += shra_ph.tst
TESTCASES += shra_pw.tst
TESTCASES += shra_qh.tst
#TESTCASES += shra_r_ob.tst
TESTCASES += shra_r_ph.tst
TESTCASES += shra_r_pw.tst
TESTCASES += shra_r_qh.tst
TESTCASES += shra_r_w.tst
TESTCASES += shrav_ph.tst
TESTCASES += shrav_pw.tst
TESTCASES += shrav_qh.tst
TESTCASES += shrav_r_ph.tst
TESTCASES += shrav_r_pw.tst
TESTCASES += shrav_r_qh.tst
TESTCASES += shrav_r_w.tst
TESTCASES += shrl_ob.tst
TESTCASES += shrl_qb.tst
#TESTCASES += shrl_qh.tst
TESTCASES += shrlv_ob.tst
TESTCASES += shrlv_qb.tst
#TESTCASES += shrlv_qh.tst
TESTCASES += subq_ph.tst
TESTCASES += subq_pw.tst
TESTCASES += subq_qh.tst
TESTCASES += subq_s_ph.tst
TESTCASES += subq_s_pw.tst
TESTCASES += subq_s_qh.tst
TESTCASES += subq_s_w.tst
TESTCASES += subu_ob.tst
TESTCASES += subu_qb.tst
TESTCASES += subu_s_ob.tst
TESTCASES += subu_s_qb.tst
TESTCASES += wrdsp.tst
all: build
head.o : head.S
$(Q)$(CC) $(HEAD_FLAGS) -D"STACK_TOP=0xffffffff80200000" -c $< -o $@
%.o : %.S
$(CC) $(CFLAGS) -c $< -o $@
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $@
%.tst: %.o $(VECTORS_OBJ)
$(CC) $(VECTORS_OBJ) $(FLAGS) $(LDFLAGS) $< -o $@
build: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES)
check: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES)
@for case in $(TESTCASES); do \
echo $(SIM) $(SIMFLAGS) ./$$case; \
$(SIM) $(SIMFLAGS) ./$$case & (sleep 1; killall $(SIM)); \
done
clean:
$(Q)rm -f *.o *.tst *.a

63
tests/tcg/mips/mips64-dsp/absq_s_ob.c
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@ -1,63 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rt, result, dspcontrol;
rt = 0x7F7F7F7F7F7F7F7F;
result = 0x7F7F7F7F7F7F7F7F;
__asm
(".set mips64\n\t"
"absq_s.ob %0 %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (result != rd) {
printf("absq_s.ob test 1 error\n");
return -1;
}
__asm
("rddsp %0\n\t"
: "=r"(rd)
);
rd >> 20;
rd = rd & 0x1;
if (rd != 0) {
printf("absq_s.ob test 1 dspcontrol overflow flag error\n");
return -1;
}
rt = 0x80FFFFFFFFFFFFFF;
result = 0x7F01010101010101;
__asm
("absq_s.ob %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (result != rd) {
printf("absq_s.ob test 2 error\n");
return -1;
}
__asm
("rddsp %0\n\t"
: "=r"(rd)
);
rd = rd >> 20;
rd = rd & 0x1;
if (rd != 1) {
printf("absq_s.ob test 2 dspcontrol overflow flag error\n");
return -1;
}
return 0;
}

37
tests/tcg/mips/mips64-dsp/absq_s_ph.c
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@ -1,37 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rt;
long long result;
rt = 0x10017EFD;
result = 0x10017EFD;
__asm
("absq_s.ph %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (rd != result) {
printf("absq_s.ph wrong\n");
return -1;
}
rt = 0x8000A536;
result = 0x7FFF5ACA;
__asm
("absq_s.ph %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (rd != result) {
printf("absq_s.ph wrong\n");
return -1;
}
return 0;
}

66
tests/tcg/mips/mips64-dsp/absq_s_pw.c
View File

@ -1,66 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rt, result, dspcontrol;
rd = 0;
rt = 0x7F7F7F7F7F7F7F7F;
result = 0x7F7F7F7F7F7F7F7F;
__asm
("absq_s.pw %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (result != rd) {
printf("absq_s.pw test 1 error\n");
return -1;
}
rd = 0;
__asm
("rddsp %0\n\t"
: "=r"(rd)
);
rd >> 20;
rd = rd & 0x1;
if (rd != 0) {
printf("absq_s.pw test 1 dspcontrol overflow flag error\n");
return -1;
}
rd = 0;
rt = 0x80000000FFFFFFFF;
result = 0x7FFFFFFF00000001;
__asm
("absq_s.pw %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (result != rd) {
printf("absq_s.pw test 2 error\n");
return -1;
}
rd = 0;
__asm
("rddsp %0\n\t"
: "=r"(rd)
);
rd = rd >> 20;
rd = rd & 0x1;
if (rd != 1) {
printf("absq_s.pw test 2 dspcontrol overflow flag error\n");
return -1;
}
return 0;
}

40
tests/tcg/mips/mips64-dsp/absq_s_qh.c
View File

@ -1,40 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rt, result, dspcontrol;
rd = 0;
rt = 0x7F7F7F7F7F7F7F7F;
result = 0x7F7F7F7F7F7F7F7F;
__asm
("absq_s.qh %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (result != rd) {
printf("absq_s.qh test 1 error\n");
return -1;
}
rd = 0;
rt = 0x8000FFFFFFFFFFFF;
result = 0x7FFF000100000001;
__asm
("absq_s.pw %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (result != rd) {
printf("absq_s.rw test 2 error\n");
return -1;
}
return 0;
}

48
tests/tcg/mips/mips64-dsp/absq_s_w.c
View File

@ -1,48 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rt;
long long result;
rt = 0x80000000;
result = 0x7FFFFFFF;
__asm
("absq_s.w %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (rd != result) {
printf("absq_s_w.ph wrong\n");
return -1;
}
rt = 0x80030000;
result = 0x7FFD0000;
__asm
("absq_s.w %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (rd != result) {
printf("absq_s_w.ph wrong\n");
return -1;
}
rt = 0x31036080;
result = 0x31036080;
__asm
("absq_s.w %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (rd != result) {
printf("absq_s_w.ph wrong\n");
return -1;
}
return 0;
}

57
tests/tcg/mips/mips64-dsp/addq_ph.c
View File

@ -1,57 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long dsp;
long long result;
rs = 0xFFFFFFFF;
rt = 0x10101010;
result = 0x100F100F;
__asm
("addq.ph %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("1 addq.ph wrong\n");
return -1;
}
rs = 0x3712847D;
rt = 0x0031AF2D;
result = 0x374333AA;
__asm
("addq.ph %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("2 addq.ph wrong\n");
return -1;
}
rs = 0x7fff847D;
rt = 0x0031AF2D;
result = 0xffffffff803033AA;
__asm
("addq.ph %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
__asm("rddsp %0\n\t"
: "=r"(dsp)
);
if (rd != result || (((dsp >> 20) & 0x01) != 1)) {
printf("3 addq.ph wrong\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/addq_pw.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result, dspreg, dspresult;
rs = 0x123456787FFFFFFF;
rt = 0x1111111100000101;
result = 0x2345678980000100;
dspresult = 0x1;
__asm
("addq.pw %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addq.pw error\n");
return -1;
}
rs = 0x1234567880FFFFFF;
rt = 0x1111111180000001;
result = 0x2345678901000000;
dspresult = 0x1;
__asm
("addq.pw %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addq.pw error\n");
return -1;
}
return 0;
}

28
tests/tcg/mips/mips64-dsp/addq_qh.c
View File

@ -1,28 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result, dspreg, dspresult;
rs = 0x123456787FFF8010;
rt = 0x1111111100018000;
result = 0x2345678980000010;
dspresult = 0x1;
__asm
("addq.qh %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addq.qh error\n");
return -1;
}
return 0;
}

84
tests/tcg/mips/mips64-dsp/addq_s_ph.c
View File

@ -1,84 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long dsp;
long long result;
rs = 0xFFFFFFFF;
rt = 0x10101010;
result = 0x100F100F;
__asm
("addq_s.ph %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("1 addq_s.ph wrong\n");
return -1;
}
rs = 0x3712847D;
rt = 0x0031AF2D;
result = 0x37438000;
__asm
("addq_s.ph %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
__asm
("rddsp %0\n\t"
: "=r"(dsp)
);
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
printf("2 addq_s.ph wrong\n");
return -1;
}
rs = 0x7fff847D;
rt = 0x0031AF2D;
result = 0x7fff8000;
__asm
("addq_s.ph %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
__asm
("rddsp %0\n\t"
: "=r"(dsp)
);
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
printf("3 addq_s.ph wrong\n");
return -1;
}
rs = 0x8030847D;
rt = 0x8a00AF2D;
result = 0xffffffff80008000;
__asm
("addq_s.ph %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
__asm
("rddsp %0\n\t"
: "=r"(dsp)
);
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
printf("4 addq_s.ph wrong\n");
return -1;
}
return 0;
}

45
tests/tcg/mips/mips64-dsp/addq_s_pw.c
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@ -1,45 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result, dspreg, dspresult;
rs = 0x123456787FFFFFFF;
rt = 0x1111111100000001;
result = 0x234567897FFFFFFF;
dspresult = 0x1;
__asm
("addq_s.pw %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addq_s.pw error\n");
return -1;
}
rs = 0x80FFFFFFE00000FF;
rt = 0x80000001200000DD;
result = 0x80000000000001DC;
dspresult = 0x01;
__asm
("addq_s.pw %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addq_s.pw error\n");
return -1;
}
return 0;
}

26
tests/tcg/mips/mips64-dsp/addq_s_qh.c
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@ -1,26 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result, dspreg, dspresult;
rs = 0x123456787FFF8000;
rt = 0x1111111100028000;
result = 0x234567897FFF8000;
dspresult = 0x1;
__asm
("addq_s.qh %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addq_s.qh error\n");
return -1;
}
return 0;
}

48
tests/tcg/mips/mips64-dsp/addq_s_w.c
View File

@ -1,48 +0,0 @@
#include "io.h"
int main()
{
long long rd, rs, rt;
long long result;
rt = 0x10017EFD;
rs = 0x11111111;
result = 0x2112900e;
__asm
("addq_s.w %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("addq_s.w error\n");
}
rt = 0x80017EFD;
rs = 0x81111111;
result = 0xffffffff80000000;
__asm
("addq_s.w %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("addq_s.w error\n");
}
rt = 0x7fffffff;
rs = 0x01111111;
result = 0x7fffffff;
__asm
("addq_s.w %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("addq_s.w error\n");
}
return 0;
}

39
tests/tcg/mips/mips64-dsp/addsc.c
View File

@ -1,39 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long dsp;
long long result;
rs = 0x0000000F;
rt = 0x00000001;
result = 0x00000010;
__asm
("addsc %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("1 addsc wrong\n");
return -1;
}
rs = 0xFFFF0FFF;
rt = 0x00010111;
result = 0x00001110;
__asm
("addsc %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rs), "r"(rt)
);
if ((rd != result) || (((dsp >> 13) & 0x01) != 1)) {
printf("2 addsc wrong\n");
return -1;
}
return 0;
}

28
tests/tcg/mips/mips64-dsp/addu_ob.c
View File

@ -1,28 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x3456123498DEF390;
result = 0x468A68AC329AD180;
dspresult = 0x01;
__asm
("addu.ob %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addu.ob error\n\t");
return -1;
}
return 0;
}

40
tests/tcg/mips/mips64-dsp/addu_qb.c
View File

@ -1,40 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long dsp;
long long result;
rs = 0x00FF00FF;
rt = 0x00010001;
result = 0x00000000;
__asm
("addu.qb %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rs), "r"(rt)
);
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
printf("1 addu.qb wrong\n");
return -1;
}
rs = 0xFFFF1111;
rt = 0x00020001;
result = 0xFFFFFFFFFF011112;
__asm
("addu.qb %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rs), "r"(rt)
);
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
printf("2 addu.qb wrong\n");
return -1;
}
return 0;
}

27
tests/tcg/mips/mips64-dsp/addu_s_ob.c
View File

@ -1,27 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x3456123498DEF390;
result = 0x468A68ACFFFFFFFF;
dspresult = 0x01;
__asm
("addu_s.ob %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 20) & 0x01);
if ((rd != result) || (dspreg != dspresult)) {
printf("addu_s.ob error\n\t");
return -1;
}
return 0;
}

40
tests/tcg/mips/mips64-dsp/addu_s_qb.c
View File

@ -1,40 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long dsp;
long long result;
rs = 0x10FF01FF;
rt = 0x10010001;
result = 0x20FF01FF;
__asm
("addu_s.qb %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rs), "r"(rt)
);
if ((rd != result) || (((dsp >> 20) & 0x1) != 1)) {
printf("1 addu_s.qb error 1\n");
return -1;
}
rs = 0xFFFFFFFFFFFF1111;
rt = 0x00020001;
result = 0xFFFFFFFFFFFF1112;
__asm
("addu_s.qb %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rs), "r"(rt)
);
if ((rd != result) || (((dsp >> 20) & 0x1) != 1)) {
printf("2 addu_s.qb error 2\n");
return -1;
}
return 0;
}

59
tests/tcg/mips/mips64-dsp/addwc.c
View File

@ -1,59 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long dspi, dspo;
long long result;
rs = 0x10FF01FF;
rt = 0x10010001;
dspi = 0x00002000;
result = 0x21000201;
__asm
("wrdsp %3\n"
"addwc %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt), "r"(dspi)
);
if (rd != result) {
printf("1 addwc wrong\n");
return -1;
}
rs = 0xFFFF1111;
rt = 0x00020001;
dspi = 0x00;
result = 0x00011112;
__asm
("wrdsp %3\n"
"addwc %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt), "r"(dspi)
);
if (rd != result) {
printf("2 addwc wrong\n");
return -1;
}
rs = 0x8FFF1111;
rt = 0x80020001;
dspi = 0x00;
result = 0x10011112;
__asm
("wrdsp %4\n"
"addwc %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dspo)
: "r"(rs), "r"(rt), "r"(dspi)
);
if ((rd != result) || (((dspo >> 20) & 0x01) != 1)) {
printf("3 addwc wrong\n");
return -1;
}
return 0;
}

23
tests/tcg/mips/mips64-dsp/bitrev.c
View File

@ -1,23 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rt;
long long result;
rt = 0x12345678;
result = 0x00001E6A;
__asm
("bitrev %0, %1\n\t"
: "=r"(rd)
: "r"(rt)
);
if (rd != result) {
printf("bitrev wrong\n");
return -1;
}
return 0;
}

50
tests/tcg/mips/mips64-dsp/bposge32.c
View File

@ -1,50 +0,0 @@
#include "io.h"
int main(void)
{
long long dsp, sum;
long long result;
dsp = 0x20;
sum = 0x01;
result = 0x02;
__asm
("wrdsp %1\n\t"
"bposge32 test1\n\t"
"nop\n\t"
"addi %0, 0xA2\n\t"
"nop\n\t"
"test1:\n\t"
"addi %0, 0x01\n\t"
: "+r"(sum)
: "r"(dsp)
);
if (sum != result) {
printf("bposge32 wrong\n");
return -1;
}
dsp = 0x10;
sum = 0x01;
result = 0xA4;
__asm
("wrdsp %1\n\t"
"bposge32 test2\n\t"
"nop\n\t"
"addi %0, 0xA2\n\t"
"nop\n\t"
"test2:\n\t"
"addi %0, 0x01\n\t"
: "+r"(sum)
: "r"(dsp)
);
if (sum != result) {
printf("bposge32 wrong\n");
return -1;
}
return 0;
}

50
tests/tcg/mips/mips64-dsp/bposge64.c
View File

@ -1,50 +0,0 @@
#include "io.h"
int main(void)
{
long long dsp, sum;
long long result;
dsp = 0x40;
sum = 0x01;
result = 0x02;
__asm
("wrdsp %1\n\t"
"bposge64 test1\n\t"
"nop\n\t"
"addi %0, 0xA2\n\t"
"nop\n\t"
"test1:\n\t"
"addi %0, 0x01\n\t"
: "+r"(sum)
: "r"(dsp)
);
if (sum != result) {
printf("bposge64 wrong\n");
return -1;
}
dsp = 0x10;
sum = 0x01;
result = 0xA4;
__asm
("wrdsp %1\n\t"
"bposge64 test2\n\t"
"nop\n\t"
"addi %0, 0xA2\n\t"
"nop\n\t"
"test2:\n\t"
"addi %0, 0x01\n\t"
: "+r"(sum)
: "r"(dsp)
);
if (sum != result) {
printf("bposge64 wrong\n");
return -1;
}
return 0;
}

42
tests/tcg/mips/mips64-dsp/cmp_eq_ph.c
View File

@ -1,42 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long result;
rs = 0x11777066;
rt = 0x55AA33FF;
result = 0x00;
__asm
("cmp.eq.ph %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
rd = (rd >> 24) & 0x03;
if (rd != result) {
printf("cmp.eq.ph wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11777066;
result = 0x03;
__asm
("cmp.eq.ph %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
rd = (rd >> 24) & 0x03;
if (rd != result) {
printf("cmp.eq.ph wrong\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/cmp_eq_pw.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEFF;
rt = 0x123456789ABCDEFF;
dspresult = 0x03;
__asm
("cmp.eq.pw %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x03);
if (dspreg != dspresult) {
printf("1 cmp.eq.pw error\n");
return -1;
}
rs = 0x123456799ABCDEFe;
rt = 0x123456789ABCDEFF;
dspresult = 0x00;
__asm
("cmp.eq.pw %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x03);
if (dspreg != dspresult) {
printf("2 cmp.eq.pw error\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/cmp_eq_qh.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x0E;
__asm
("cmp.eq.qh %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x0F);
if (dspreg != dspresult) {
printf("cmp.eq.qh error\n");
return -1;
}
rs = 0x12355a789A4CD3F0;
rt = 0x123456789ABCDEFF;
dspresult = 0x00;
__asm
("cmp.eq.qh %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x0F);
if (dspreg != dspresult) {
printf("cmp.eq.qh error\n");
return -1;
}
return 0;
}

40
tests/tcg/mips/mips64-dsp/cmp_le_ph.c
View File

@ -1,40 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long result;
rs = 0x11777066;
rt = 0x55AA33FF;
result = 0x02;
__asm
("cmp.le.ph %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
rd = (rd >> 24) & 0x03;
if (rd != result) {
printf("cmp.le.ph wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11777066;
result = 0x03;
__asm
("cmp.le.ph %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
rd = (rd >> 24) & 0x03;
if (rd != result) {
printf("cmp.le.ph wrong\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/cmp_le_pw.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x03;
__asm
("cmp.le.pw %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x03);
if (dspreg != dspresult) {
printf("1 cmp.le.pw error\n");
return -1;
}
rs = 0x123456799ABCEEFF;
rt = 0x123456789ABCDEFF;
dspresult = 0x00;
__asm
("cmp.le.pw %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x03);
if (dspreg != dspresult) {
printf("2 cmp.le.pw error\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/cmp_le_qh.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x0F;
__asm
("cmp.le.qh %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x0F);
if (dspreg != dspresult) {
printf("cmp.le.qh error\n");
return -1;
}
rs = 0x823456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x0f;
__asm
("cmp.le.qh %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x0F);
if (dspreg != dspresult) {
printf("cmp.le.qh error\n");
return -1;
}
return 0;
}

41
tests/tcg/mips/mips64-dsp/cmp_lt_ph.c
View File

@ -1,41 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long result;
rs = 0x11777066;
rt = 0x55AA33FF;
result = 0x02;
__asm
("cmp.lt.ph %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
rd = (rd >> 24) & 0x03;
if (rd != result) {
printf("cmp.lt.ph wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11777066;
result = 0x00;
__asm
("cmp.lt.ph %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
rd = (rd >> 24) & 0x03;
if (rd != result) {
printf("cmp.lt.ph2 wrong\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/cmp_lt_pw.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x01;
__asm
("cmp.lt.pw %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x03);
if (dspreg != dspresult) {
printf("cmp.lt.pw error\n");
return -1;
}
rs = 0x123456779ABCDEFf;
rt = 0x123456789ABCDEFF;
dspresult = 0x02;
__asm
("cmp.lt.pw %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x03);
if (dspreg != dspresult) {
printf("cmp.lt.pw error\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/cmp_lt_qh.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123558789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x01;
__asm
("cmp.lt.qh %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x0F);
if (dspreg != dspresult) {
printf("cmp.lt.qh error\n");
return -1;
}
rs = 0x123356779ABbDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x0f;
__asm
("cmp.lt.qh %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0x0F);
if (dspreg != dspresult) {
printf("cmp.lt.qh error\n");
return -1;
}
return 0;
}

40
tests/tcg/mips/mips64-dsp/cmpgu_eq_ob.c
View File

@ -1,40 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
result = 0xFE;
__asm
("cmpgu.eq.ob %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.eq.ob error\n");
return -1;
}
rs = 0x133456789ABCDEF0;
rt = 0x123556789ABCDEFF;
result = 0x3E;
__asm
("cmpgu.eq.ob %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.eq.ob error\n");
return -1;
}
return 0;
}

38
tests/tcg/mips/mips64-dsp/cmpgu_eq_qb.c
View File

@ -1,38 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long result;
rs = 0x11777066;
rt = 0x55AA70FF;
result = 0x02;
__asm
("cmpgu.eq.qb %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.eq.ph wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11777066;
result = 0x0F;
__asm
("cmpgu.eq.qb %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.eq.ph wrong\n");
return -1;
}
return 0;
}

40
tests/tcg/mips/mips64-dsp/cmpgu_le_ob.c
View File

@ -1,40 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
result = 0xFF;
__asm
("cmpgu.le.ob %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.le.ob error\n");
return -1;
}
rs = 0x823556789ABCDEF0;
rt = 0x123456789ABCDEFF;
result = 0x3F;
__asm
("cmpgu.le.ob %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.le.ob error\n");
return -1;
}
return 0;
}

37
tests/tcg/mips/mips64-dsp/cmpgu_le_qb.c
View File

@ -1,37 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long result;
rs = 0x11777066;
rt = 0x55AA70FF;
result = 0x0F;
__asm
("cmpgu.le.qb %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.le.qb wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11766066;
result = 0x09;
__asm
("cmpgu.le.qb %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.le.qb wrong\n");
return -1;
}
return 0;
}

40
tests/tcg/mips/mips64-dsp/cmpgu_lt_ob.c
View File

@ -1,40 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, result;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
result = 0x01;
__asm
("cmpgu.lt.ob %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.lt.ob error\n");
return -1;
}
rs = 0x823455789ABCDEF0;
rt = 0x123356789ABCDEFF;
result = 0x21;
__asm
("cmpgu.lt.ob %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.lt.ob error\n");
return -1;
}
return 0;
}

38
tests/tcg/mips/mips64-dsp/cmpgu_lt_qb.c
View File

@ -1,38 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt;
long long result;
rs = 0x11777066;
rt = 0x55AA70FF;
result = 0x0D;
__asm
("cmpgu.lt.qb %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.lt.qb wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11766066;
result = 0x00;
__asm
("cmpgu.lt.qb %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
if (rd != result) {
printf("cmpgu.lt.qb wrong\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/cmpu_eq_ob.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rd, rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0xFE;
__asm
("cmpu.eq.ob %1, %2\n\t"
"rddsp %0"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0xFF);
if (dspreg != dspresult) {
printf("cmpu.eq.ob error\n");
return -1;
}
rs = 0x133516713A0CD1F0;
rt = 0x123456789ABCDEFF;
dspresult = 0x00;
__asm
("cmpu.eq.ob %1, %2\n\t"
"rddsp %0"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = ((dspreg >> 24) & 0xFF);
if (dspreg != dspresult) {
printf("cmpu.eq.ob error\n");
return -1;
}
return 0;
}

42
tests/tcg/mips/mips64-dsp/cmpu_eq_qb.c
View File

@ -1,42 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long dsp;
long long result;
rs = 0x11777066;
rt = 0x55AA70FF;
result = 0x02;
__asm
("cmpu.eq.qb %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 24) & 0x0F;
if (dsp != result) {
printf("cmpu.eq.qb wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11777066;
result = 0x0F;
__asm
("cmpu.eq.qb %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 24) & 0x0F;
if (dsp != result) {
printf("cmpu.eq.qb wrong\n");
return -1;
}
return 0;
}

44
tests/tcg/mips/mips64-dsp/cmpu_le_ob.c
View File

@ -1,44 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0xFF;
__asm
("cmpu.le.ob %1, %2\n\t"
"rddsp %0"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = dspreg >> 24;
if (dspreg != dspresult) {
printf("cmpu.le.ob error\n");
return -1;
}
rs = 0x823656789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x3F;
__asm
("cmpu.le.ob %1, %2\n\t"
"rddsp %0"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = dspreg >> 24;
if (dspreg != dspresult) {
printf("cmpu.le.ob error\n");
return -1;
}
return 0;
}

41
tests/tcg/mips/mips64-dsp/cmpu_le_qb.c
View File

@ -1,41 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long dsp;
long long result;
rs = 0x11777066;
rt = 0x55AA70FF;
result = 0x0F;
__asm
("cmpu.le.qb %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 24) & 0x0F;
if (dsp != result) {
printf("cmpu.le.qb wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11777066;
result = 0x0F;
__asm
("cmpu.le.qb %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 24) & 0x0F;
if (dsp != result) {
printf("cmpu.le.qb wrong\n");
return -1;
}
return 0;
}

44
tests/tcg/mips/mips64-dsp/cmpu_lt_ob.c
View File

@ -1,44 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dspreg, dspresult;
rs = 0x123456789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x01;
__asm
("cmpu.lt.ob %1, %2\n\t"
"rddsp %0"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = dspreg >> 24;
if (dspreg != dspresult) {
printf("cmpu.lt.ob error\n");
return -1;
}
rs = 0x823156789ABCDEF0;
rt = 0x123456789ABCDEFF;
dspresult = 0x41;
__asm
("cmpu.lt.ob %1, %2\n\t"
"rddsp %0"
: "=r"(dspreg)
: "r"(rs), "r"(rt)
);
dspreg = dspreg >> 24;
if (dspreg != dspresult) {
printf("cmpu.lt.ob error\n");
return -1;
}
return 0;
}

42
tests/tcg/mips/mips64-dsp/cmpu_lt_qb.c
View File

@ -1,42 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long dsp;
long long result;
rs = 0x11777066;
rt = 0x55AA70FF;
result = 0x0D;
__asm
("cmpu.lt.qb %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 24) & 0x0F;
if (dsp != result) {
printf("cmpu.lt.qb wrong\n");
return -1;
}
rs = 0x11777066;
rt = 0x11777066;
result = 0x00;
__asm
("cmpu.lt.qb %1, %2\n\t"
"rddsp %0\n\t"
: "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 24) & 0x0F;
if (dsp != result) {
printf("cmpu.lt.qb wrong\n");
return -1;
}
return 0;
}

37
tests/tcg/mips/mips64-dsp/dappend.c
View File

@ -1,37 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs;
long long res;
rt = 0x1234567887654321;
rs = 0xabcd1234abcd8765;
res = 0x1234567887654321;
__asm
("dappend %0, %1, 0x0\n\t"
: "=r"(rt)
: "r"(rs)
);
if (rt != res) {
printf("dappend error\n");
return -1;
}
rt = 0x1234567887654321;
rs = 0xabcd1234abcd8765;
res = 0x2345678876543215;
__asm
("dappend %0, %1, 0x4\n\t"
: "=r"(rt)
: "r"(rs)
);
if (rt != res) {
printf("dappend error\n");
return -1;
}
return 0;
}

54
tests/tcg/mips/mips64-dsp/dextp.c
View File

@ -1,54 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp;
long long achi, acli;
long long res, resdsp;
int rs;
rs = 0xabcd1234;
achi = 0x12345678;
acli = 0x87654321;
res = 0xff;
resdsp = 0x0;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4\n\t"
"dextp %0, $ac1, 0x7\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 14) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextp error\n");
return -1;
}
rs = 0xabcd1200;
achi = 0x12345678;
acli = 0x87654321;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4\n\t"
"dextp %0, $ac1, 0x7\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 14) & 0x1;
if (dsp != resdsp) {
printf("dextp error\n");
return -1;
}
return 0;
}

59
tests/tcg/mips/mips64-dsp/dextpdp.c
View File

@ -1,59 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp;
long long achi, acli;
long long res, resdsp, resdsppos;
int rs;
int tmp1, tmp2;
rs = 0xabcd1234;
achi = 0x12345678;
acli = 0x87654321;
res = 0xff;
resdsp = 0x0;
resdsppos = 0x2c;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4\n\t"
"dextpdp %0, $ac1, 0x7\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
tmp1 = (dsp >> 14) & 0x1;
tmp2 = dsp & 0x3f;
if ((tmp1 != resdsp) || (rt != res) || (tmp2 != resdsppos)) {
printf("dextpdp error\n");
return -1;
}
rs = 0xabcd1200;
achi = 0x12345678;
acli = 0x87654321;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4\n\t"
"dextpdp %0, $ac1, 0x7\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
tmp1 = (dsp >> 14) & 0x1;
if (tmp1 != resdsp) {
printf("dextpdp error\n");
return -1;
}
return 0;
}

63
tests/tcg/mips/mips64-dsp/dextpdpv.c
View File

@ -1,63 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs, dsp;
long long achi, acli;
long long res, resdsp, resdsppos;
int rsdsp;
int tmp1, tmp2;
rsdsp = 0xabcd1234;
rs = 0x7;
achi = 0x12345678;
acli = 0x87654321;
res = 0xff;
resdsp = 0x0;
resdsppos = 0x2c;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4, 0x1\n\t"
"wrdsp %4\n\t"
"dextpdpv %0, $ac1, %5\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs)
);
tmp1 = (dsp >> 14) & 0x1;
tmp2 = dsp & 0x3f;
if ((tmp1 != resdsp) || (rt != res) || (tmp2 != resdsppos)) {
printf("dextpdpv error\n");
return -1;
}
rsdsp = 0xabcd1200;
rs = 0x7;
achi = 0x12345678;
acli = 0x87654321;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4, 0x1\n\t"
"wrdsp %4\n\t"
"dextpdpv %0, $ac1, %5\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs)
);
tmp1 = (dsp >> 14) & 0x1;
if (tmp1 != resdsp) {
printf("dextpdpv error\n");
return -1;
}
return 0;
}

58
tests/tcg/mips/mips64-dsp/dextpv.c
View File

@ -1,58 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs, dsp;
long long achi, acli;
long long res, resdsp;
int rsdsp;
rsdsp = 0xabcd1234;
rs = 0x7;
achi = 0x12345678;
acli = 0x87654321;
res = 0xff;
resdsp = 0x0;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4, 0x1\n\t"
"wrdsp %4\n\t"
"dextpv %0, $ac1, %5\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs)
);
dsp = (dsp >> 14) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextpv error\n");
return -1;
}
rsdsp = 0xabcd1200;
rs = 0x7;
achi = 0x12345678;
acli = 0x87654321;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"wrdsp %4, 0x1\n\t"
"wrdsp %4\n\t"
"dextpv %0, $ac1, %5\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs)
);
dsp = (dsp >> 14) & 0x1;
if (dsp != resdsp) {
printf("dextpv error\n");
return -1;
}
return 0;
}

44
tests/tcg/mips/mips64-dsp/dextr_l.c
View File

@ -1,44 +0,0 @@
#include "io.h"
int main(void)
{
long long rt;
long long achi, acli;
long long res;
achi = 0x87654321;
acli = 0x12345678;
res = 0x2100000000123456;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextr.l %0, $ac1, 0x8\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli)
);
if (rt != res) {
printf("dextr.l error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
res = 0x12345678;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextr.l %0, $ac1, 0x0\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli)
);
if (rt != res) {
printf("dextr.l error\n");
return -1;
}
return 0;
}

54
tests/tcg/mips/mips64-dsp/dextr_r_l.c
View File

@ -1,54 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
res = 0x2100000000123456;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_r.l %0, $ac1, 0x8\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_r.l error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
res = 0x12345678;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_r.l %0, $ac1, 0x0\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_r.l error\n");
return -1;
}
return 0;
}

54
tests/tcg/mips/mips64-dsp/dextr_r_w.c
View File

@ -1,54 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
res = 0x123456;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_r.w %0, $ac1, 0x8\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_r.w error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
res = 0x12345678;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_r.w %0, $ac1, 0x0\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_r.w error\n");
return -1;
}
return 0;
}

52
tests/tcg/mips/mips64-dsp/dextr_rs_l.c
View File

@ -1,52 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
res = 0x8000000000000000;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_rs.l %0, $ac1, 0x8\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_rs.l error\n");
return -1;
}
achi = 0x00;
acli = 0x12345678;
res = 0x12345678;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_rs.l %0, $ac1, 0x0\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_rs.l error\n");
return -1;
}
return 0;
}

52
tests/tcg/mips/mips64-dsp/dextr_rs_w.c
View File

@ -1,52 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
res = 0xffffffff80000000;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_rs.w %0, $ac1, 0x8\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_rs.w error\n");
return -1;
}
achi = 0x00;
acli = 0x12345678;
res = 0x123456;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_rs.w %0, $ac1, 0x8\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextr_rs.w error\n");
return -1;
}
return 0;
}

73
tests/tcg/mips/mips64-dsp/dextr_s_h.c
View File

@ -1,73 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
res = 0xffffffffffff8000;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_s.h %0, $ac1, 0x8\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("1 dextr_s.h error\n");
return -1;
}
achi = 0x77654321;
acli = 0x12345678;
res = 0x7fff;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_s.h %0, $ac1, 0x8\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("2 dextr_s.h error\n");
return -1;
}
achi = 0x00;
acli = 0x78;
res = 0x7;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextr_s.h %0, $ac1, 0x4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("3 dextr_s.h error\n");
return -1;
}
return 0;
}

44
tests/tcg/mips/mips64-dsp/dextr_w.c
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@ -1,44 +0,0 @@
#include "io.h"
int main(void)
{
long long rt;
long long achi, acli;
long long res;
achi = 0x87654321;
acli = 0x12345678;
res = 0x123456;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextr.w %0, $ac1, 0x8\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli)
);
if (rt != res) {
printf("dextr.w error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
res = 0x12345678;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextr.w %0, $ac1, 0x0\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli)
);
if (rt != res) {
printf("dextr.w error\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/dextrv_l.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs;
long long achi, acli;
long long res;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x8;
res = 0x2100000000123456;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextrv.l %0, $ac1, %3\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli), "r"(rs)
);
if (rt != res) {
printf("dextrv.l error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
rs = 0x0;
res = 0x12345678;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextrv.l %0, $ac1, %3\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli), "r"(rs)
);
if (rt != res) {
printf("dextrv.l error\n");
return -1;
}
return 0;
}

56
tests/tcg/mips/mips64-dsp/dextrv_r_l.c
View File

@ -1,56 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, dsp, rs;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x8;
res = 0x2100000000123456;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_r.l %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_r.l error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
rs = 0x0;
res = 0x12345678;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_r.l %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_r.l error\n");
return -1;
}
return 0;
}

56
tests/tcg/mips/mips64-dsp/dextrv_r_w.c
View File

@ -1,56 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x8;
res = 0x123456;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_r.w %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_r.w error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
rs = 0x0;
res = 0x12345678;
resdsp = 0x01;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_r.w %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_r.w error\n");
return -1;
}
return 0;
}

54
tests/tcg/mips/mips64-dsp/dextrv_rs_l.c
View File

@ -1,54 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x8;
res = 0x8000000000000000;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_rs.l %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_rs.l error\n");
return -1;
}
achi = 0x00;
acli = 0x12345678;
rs = 0x0;
res = 0x12345678;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_rs.l %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_rs.l error\n");
return -1;
}
return 0;
}

54
tests/tcg/mips/mips64-dsp/dextrv_rs_w.c
View File

@ -1,54 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x8;
res = 0xffffffff80000000;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_rs.w %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_rs.w error\n");
return -1;
}
achi = 0x00;
acli = 0x12345678;
rs = 0x8;
res = 0x123456;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_rs.w %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_rs.w error\n");
return -1;
}
return 0;
}

32
tests/tcg/mips/mips64-dsp/dextrv_s_h.c
View File

@ -1,32 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs, dsp;
long long achi, acli;
long long res, resdsp;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x8;
res = 0xffffffffffff8000;
resdsp = 0x1;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dextrv_s.h %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs)
);
dsp = (dsp >> 23) & 0x1;
if ((dsp != resdsp) || (rt != res)) {
printf("dextrv_s.h error\n");
return -1;
}
return 0;
}

46
tests/tcg/mips/mips64-dsp/dextrv_w.c
View File

@ -1,46 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs;
long long achi, acli;
long long res;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x8;
res = 0x123456;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextrv.w %0, $ac1, %3\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli), "r"(rs)
);
if (rt != res) {
printf("dextrv.w error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
rs = 0x0;
res = 0x12345678;
__asm
("mthi %1, $ac1\n\t"
"mtlo %2, $ac1\n\t"
"dextrv.w %0, $ac1, %3\n\t"
: "=r"(rt)
: "r"(achi), "r"(acli), "r"(rs)
);
if (rt != res) {
printf("dextrv.w error\n");
return -1;
}
return 0;
}

26
tests/tcg/mips/mips64-dsp/dinsv.c
View File

@ -1,26 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dsp;
long long res;
rs = 0x1234567887654321;
rt = 0x1234567812345678;
dsp = 0x2222;
res = 0x1234567812345678;
__asm
("wrdsp %1, 0x3\n\t"
"wrdsp %1\n\t"
"dinsv %0, %2\n\t"
: "+r"(rt)
: "r"(dsp), "r"(rs)
);
if (rt != res) {
printf("dinsv error\n");
return -1;
}
return 0;
}

57
tests/tcg/mips/mips64-dsp/dmadd.c
View File

@ -1,57 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
achi = 0x1;
acli = 0x1;
rs = 0x0000000100000001;
rt = 0x0000000200000002;
resh = 0x1;
resl = 0x5;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmadd $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dmadd error\n");
return -1;
}
achi = 0x1;
acli = 0x1;
rs = 0xaaaabbbbccccdddd;
rt = 0xaaaabbbbccccdddd;
resh = 0x0000000000000000;
resl = 0xffffffffca860b63;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmadd $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("2 dmadd error\n");
return -1;
}
return 0;
}

56
tests/tcg/mips/mips64-dsp/dmaddu.c
View File

@ -1,56 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
achi = 0x1;
acli = 0x2;
rs = 0x0000000200000002;
rt = 0x0000000200000002;
resh = 0x1;
resl = 0xa;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmaddu $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dmaddu error\n");
return -1;
}
achi = 0x1;
acli = 0x1;
rs = 0xaaaabbbbccccdddd;
rt = 0xaaaabbbbccccdddd;
resh = 0x0000000000000002;
resl = 0xffffffffca860b63;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmaddu $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("2 dmaddu error\n");
return -1;
}
return 0;
}

59
tests/tcg/mips/mips64-dsp/dmsub.c
View File

@ -1,59 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
achi = 0x1;
acli = 0x8;
rs = 0x0000000100000001;
rt = 0x0000000200000002;
resh = 0x1;
resl = 0x4;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmsub $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dmsub error\n");
return -1;
}
achi = 0xfffffffF;
acli = 0xfffffffF;
rs = 0x8888999977776666;
rt = 0x9999888877776666;
resh = 0xffffffffffffffff;
resl = 0x789aae13;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmsub $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("2 dmsub error\n");
return -1;
}
return 0;
}

59
tests/tcg/mips/mips64-dsp/dmsubu.c
View File

@ -1,59 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
achi = 0x1;
acli = 0x8;
rs = 0x0000000100000001;
rt = 0x0000000200000002;
resh = 0x1;
resl = 0x4;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmsubu $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dmsubu error\n");
return -1;
}
achi = 0xfffffffF;
acli = 0xfffffffF;
rs = 0x8888999977776666;
rt = 0x9999888877776666;
resh = 0xffffffffffffffff;
resl = 0x789aae13;
__asm
("mthi %2, $ac1 \t\n"
"mtlo %3, $ac1 \t\n"
"dmsubu $ac1, %4, %5\t\n"
"mfhi %0, $ac1 \t\n"
"mflo %1, $ac1 \t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("2 dmsubu error\n");
return -1;
}
return 0;
}

41
tests/tcg/mips/mips64-dsp/dmthlip.c
View File

@ -1,41 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, dsp;
long long achi, acli;
long long rsdsp;
long long acho, aclo;
long long res;
long long reshi, reslo;
rs = 0xaaaabbbbccccdddd;
achi = 0x87654321;
acli = 0x12345678;
dsp = 0x22;
res = 0x62;
reshi = 0x12345678;
reslo = 0xffffffffccccdddd;
__asm
("mthi %3, $ac1\n\t"
"mtlo %4, $ac1\n\t"
"wrdsp %5\n\t"
"dmthlip %6, $ac1\n\t"
"rddsp %0\n\t"
"mfhi %1, $ac1\n\t"
"mflo %2, $ac1\n\t"
: "=r"(rsdsp), "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(dsp), "r"(rs)
);
if ((rsdsp != res) || (acho != reshi) || (aclo != reslo)) {
printf("dmthlip error\n");
return -1;
}
return 0;
}

32
tests/tcg/mips/mips64-dsp/dpaq_s_w_ph.c
View File

@ -1,32 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dsp;
long long ach = 0, acl = 0;
long long resulth, resultl, resultdsp;
rs = 0x800000FF;
rt = 0x80000002;
resulth = 0x00;
resultl = 0xFFFFFFFF800003FB;
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpaq_s.w.ph $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(ach), "+r"(acl), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = dsp >> 17 & 0x01;
if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) {
printf("dpaq_w.w.ph wrong\n");
return -1;
}
return 0;
}

57
tests/tcg/mips/mips64-dsp/dpaq_s_w_qh.c
View File

@ -1,57 +0,0 @@
#include"io.h"
int main(void)
{
long long rt, rs;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
achi = 0x1;
acli = 0x1;
rs = 0x0001000100010001;
rt = 0x0002000200020002;
resh = 0x1;
resl = 0x11;
__asm
("mthi %2, $ac1\t\n"
"mtlo %3, $ac1\t\n"
"dpaq_s.w.qh $ac1, %4, %5\t\n"
"mfhi %0, $ac1\t\n"
"mflo %1, $ac1\t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dpaq_s.w.qh error\n");
return -1;
}
achi = 0xffffffff;
acli = 0xaaaaaaaa;
rs = 0x1111222233334444;
rt = 0xffffeeeeddddcccc;
resh = 0x00;
resl = 0xffffffffd27ad82e;
__asm
("mthi %2, $ac1\t\n"
"mtlo %3, $ac1\t\n"
"dpaq_s.w.qh $ac1, %4, %5\t\n"
"mfhi %0, $ac1\t\n"
"mflo %1, $ac1\t\n"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("2 dpaq_s.w.qh error\n");
return -1;
}
return 0;
}

88
tests/tcg/mips/mips64-dsp/dpaq_sa_l_pw.c
View File

@ -1,88 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long achi, acli;
long long acho, aclo;
long long dsp;
long long resh, resl;
long long resdsp;
rs = 0x0000000100000001;
rt = 0x0000000200000002;
achi = 0x1;
acli = 0x1;
resh = 0xffffffffffffffff;
resl = 0x0;
resdsp = 0x01;
__asm
("mthi %3, $ac1\n\t"
"mtlo %4, $ac1\n\t"
"dpaq_sa.l.pw $ac1, %5, %6\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "=r"(acho), "=r"(aclo), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl) || ((dsp >> (16 + 1)) != resdsp)) {
printf("1 dpaq_sa_l_pw error\n");
return -1;
}
rs = 0xaaaabbbbccccdddd;
rt = 0x3333444455556666;
achi = 0x88888888;
acli = 0x66666666;
resh = 0xffffffff88888887;
resl = 0xffffffff9e2661da;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dpaq_sa.l.pw $ac1, %4, %5\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("2 dpaq_sa_l_pw error\n");
return -1;
}
rs = 0x8000000080000000;
rt = 0x8000000080000000;
achi = 0x88888888;
acli = 0x66666666;
resh = 0xffffffffffffffff;
resl = 0x00;
resdsp = 0x01;
__asm
("mthi %3, $ac1\n\t"
"mtlo %4, $ac1\n\t"
"dpaq_sa.l.pw $ac1, %5, %6\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "=r"(acho), "=r"(aclo), "=r"(dsp)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl) || ((dsp >> (16 + 1)) != resdsp)) {
printf("2 dpaq_sa_l_pw error\n");
return -1;
}
return 0;
}

82
tests/tcg/mips/mips64-dsp/dpaq_sa_l_w.c
View File

@ -1,82 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dsp;
long long ach = 0, acl = 0;
long long resulth, resultl, resultdsp;
rs = 0x80000000;
rt = 0x80000000;
resulth = 0x7FFFFFFF;
resultl = 0xffffffffFFFFFFFF;
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
"mtlo %0, $ac1\n\t"
"dpaq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(ach), "+r"(acl), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 17) & 0x01;
if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) {
printf("dpaq_sa.l.w error\n");
return -1;
}
ach = 0x12;
acl = 0x48;
rs = 0x80000000;
rt = 0x80000000;
resulth = 0x7FFFFFFF;
resultl = 0xffffffffFFFFFFFF;
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
"mtlo %0, $ac1\n\t"
"dpaq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(ach), "+r"(acl), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 17) & 0x01;
if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) {
printf("dpaq_sa.l.w error\n");
return -1;
}
ach = 0x741532A0;
acl = 0xfceabb08;
rs = 0x80000000;
rt = 0x80000000;
resulth = 0x7fffffff;
resultl = 0xffffffffffffffff;
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
"mtlo %0, $ac1\n\t"
"dpaq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(ach), "+r"(acl), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 17) & 0x01;
if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) {
printf("dpaq_sa.l.w error\n");
return -1;
}
return 0;
}

59
tests/tcg/mips/mips64-dsp/dpau_h_obl.c
View File

@ -1,59 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
rs = 0x0000000100000001;
rt = 0x0000000200000002;
achi = 0x1;
acli = 0x1;
resh = 0x1;
resl = 0x3;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dpau.h.obl $ac1, %4, %5\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dpau.h.obl error\n");
return -1;
}
rs = 0xaaaabbbbccccdddd;
rt = 0x3333444455556666;
achi = 0x88888888;
acli = 0x66666666;
resh = 0xffffffff88888888;
resl = 0x66670d7a;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dpau.h.obl $ac1, %4, %5\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dpau.h.obl error\n");
return -1;
}
return 0;
}

59
tests/tcg/mips/mips64-dsp/dpau_h_obr.c
View File

@ -1,59 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
rs = 0x0000000100000001;
rt = 0x0000000200000002;
achi = 0x1;
acli = 0x1;
resh = 0x1;
resl = 0x3;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dpau.h.obr $ac1, %4, %5\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dpau.h.obr error\n");
return -1;
}
rs = 0xccccddddaaaabbbb;
rt = 0x5555666633334444;
achi = 0x88888888;
acli = 0x66666666;
resh = 0xffffffff88888888;
resl = 0x66670d7a;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dpau.h.obr $ac1, %4, %5\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dpau.h.obr error\n");
return -1;
}
return 0;
}

29
tests/tcg/mips/mips64-dsp/dpau_h_qbl.c
View File

@ -1,29 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long ach = 5, acl = 3;
long long resulth, resultl;
rs = 0x800000FF;
rt = 0x80000002;
resulth = 0x05;
resultl = 0x4003;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpau.h.qbl $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("dpau.h.qbl wrong\n");
return -1;
}
return 0;
}

29
tests/tcg/mips/mips64-dsp/dpau_h_qbr.c
View File

@ -1,29 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long ach = 5, acl = 3;
long long resulth, resultl;
rs = 0x800000FF;
rt = 0x80000002;
resulth = 0x05;
resultl = 0x0201;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpau.h.qbr $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("dpau.h.qbr wrong\n");
return -1;
}
return 0;
}

51
tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c
View File

@ -1,51 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long ach = 5, acl = 5;
long long resulth, resultl;
rs = 0xBC0123AD;
rt = 0x01643721;
resulth = 0x04;
resultl = 0xFFFFFFFFEE9794A3;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsq_s.w.ph $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("1 dpsq_s.w.ph wrong\n");
return -1;
}
ach = 0x1424Ef1f;
acl = 0x1035219A;
rs = 0x800083AD;
rt = 0x80003721;
resulth = 0x1424ef1e;
resultl = 0x577ed901;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsq_s.w.ph $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("2 dpsq_s.w.ph wrong\n");
return -1;
}
return 0;
}

56
tests/tcg/mips/mips64-dsp/dpsq_s_w_qh.c
View File

@ -1,56 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long achi, acli;
long long acho, aclo;
long long resh, resl;
rs = 0xffffeeeeddddcccc;
rt = 0x9999888877776666;
achi = 0x67576;
acli = 0x98878;
resh = 0x67576;
resl = 0x5b1682c4;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dpsq_s.w.qh $ac1, %4, %5\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("1 dpsq_s.w.qh wrong\n");
return -1;
}
rs = 0x8000800080008000;
rt = 0x8000800080008000;
achi = 0x67576;
acli = 0x98878;
resh = 0x67575;
resl = 0x0009887c;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dpsq_s.w.qh $ac1, %4, %5\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs), "r"(rt)
);
if ((acho != resh) || (aclo != resl)) {
printf("2 dpsq_s.w.qh wrong\n");
return -1;
}
return 0;
}

76
tests/tcg/mips/mips64-dsp/dpsq_sa_l_pw.c
View File

@ -1,76 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dsp;
long long achi, acli;
long long resh, resl, resdsp;
rs = 0x89789BC0123AD;
rt = 0x5467591643721;
achi = 0x98765437;
acli = 0x65489709;
resh = 0xffffffffffffffff;
resl = 0x00;
resdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsq_sa.l.pw $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(achi), "+r"(acli), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 17) & 0x01;
if ((dsp != resdsp) || (achi != resh) || (acli != resl)) {
printf("1 dpsq_sa.l.pw wrong\n");
return -1;
}
/* clear dspcontrol reg for next test use. */
dsp = 0;
__asm
("wrdsp %0"
:
: "r"(dsp)
);
rs = 0x8B78980000000;
rt = 0x5867580000000;
achi = 0x98765437;
acli = 0x65489709;
resh = 0xffffffff98765436;
resl = 0x11d367d0;
resdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsq_sa.l.pw $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(achi), "+r"(acli), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 17) & 0x01;
if ((dsp != resdsp) || (achi != resh) || (acli != resl)) {
printf("2 dpsq_sa.l.pw wrong\n");
return -1;
}
return 0;
}

59
tests/tcg/mips/mips64-dsp/dpsq_sa_l_w.c
View File

@ -1,59 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt, dsp;
long long ach = 5, acl = 5;
long long resulth, resultl, resultdsp;
rs = 0xBC0123AD;
rt = 0x01643721;
resulth = 0xfffffffffdf4cbe0;
resultl = 0xFFFFFFFFd138776b;
resultdsp = 0x00;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(ach), "+r"(acl), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 17) & 0x01;
if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) {
printf("1 dpsq_sa.l.w wrong\n");
return -1;
}
ach = 0x54321123;
acl = 5;
rs = 0x80000000;
rt = 0x80000000;
resulth = 0xffffffffd4321123;
resultl = 0x06;
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
"rddsp %2\n\t"
: "+r"(ach), "+r"(acl), "=r"(dsp)
: "r"(rs), "r"(rt)
);
dsp = (dsp >> 17) & 0x01;
if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) {
printf("2 dpsq_sa.l.w wrong\n");
return -1;
}
return 0;
}

32
tests/tcg/mips/mips64-dsp/dpsu_h_obl.c
View File

@ -1,32 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long ach = 5, acl = 5;
long long resulth, resultl;
rs = 0x88886666BC0123AD;
rt = 0x9999888801643721;
resulth = 0x04;
resultl = 0xFFFFFFFFFFFEF115;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsu.h.obl $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("dpsu.h.obl wrong\n");
return -1;
}
return 0;
}

32
tests/tcg/mips/mips64-dsp/dpsu_h_obr.c
View File

@ -1,32 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long ach = 5, acl = 5;
long long resulth, resultl;
rs = 0x7878878888886666;
rt = 0x9865454399998888;
resulth = 0x04;
resultl = 0xFFFFFFFFFFFeF115;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsu.h.obr $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("dpsu.h.qbr wrong\n");
return -1;
}
return 0;
}

29
tests/tcg/mips/mips64-dsp/dpsu_h_qbl.c
View File

@ -1,29 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long ach = 5, acl = 5;
long long resulth, resultl;
rs = 0xBC0123AD;
rt = 0x01643721;
resulth = 0x04;
resultl = 0xFFFFFFFFFFFFFEE5;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsu.h.qbl $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("dpsu.h.qbl wrong\n");
return -1;
}
return 0;
}

29
tests/tcg/mips/mips64-dsp/dpsu_h_qbr.c
View File

@ -1,29 +0,0 @@
#include "io.h"
int main(void)
{
long long rs, rt;
long long ach = 5, acl = 5;
long long resulth, resultl;
rs = 0xBC0123AD;
rt = 0x01643721;
resulth = 0x04;
resultl = 0xFFFFFFFFFFFFE233;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"dpsu.h.qbr $ac1, %2, %3\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs), "r"(rt)
);
if ((ach != resulth) || (acl != resultl)) {
printf("dpsu.h.qbr wrong\n");
return -1;
}
return 0;
}

52
tests/tcg/mips/mips64-dsp/dshilo.c
View File

@ -1,52 +0,0 @@
#include "io.h"
int main(void)
{
long long achi, acli;
long long acho, aclo;
long long reshi, reslo;
achi = 0x87654321;
acli = 0x12345678;
reshi = 0xfffffffff8765432;
reslo = 0x1234567;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dshilo $ac1, 0x4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli)
);
if ((acho != reshi) || (aclo != reslo)) {
printf("1 dshilo error\n");
return -1;
}
achi = 0x87654321;
acli = 0x12345678;
reshi = 0x1234567;
reslo = 0x00;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dshilo $ac1, -60\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli)
);
if ((acho != reshi) || (aclo != reslo)) {
printf("2 dshilo error\n");
return -1;
}
return 0;
}

54
tests/tcg/mips/mips64-dsp/dshilov.c
View File

@ -1,54 +0,0 @@
#include "io.h"
int main(void)
{
long long achi, acli, rs;
long long acho, aclo;
long long reshi, reslo;
achi = 0x87654321;
acli = 0x12345678;
rs = 0x4;
reshi = 0xfffffffff8765432;
reslo = 0x1234567;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dshilov $ac1, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs)
);
if ((acho != reshi) || (aclo != reslo)) {
printf("dshilov error\n");
return -1;
}
rs = 0x44;
achi = 0x87654321;
acli = 0x12345678;
reshi = 0x1234567;
reslo = 0x00;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"dshilov $ac1, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "=r"(acho), "=r"(aclo)
: "r"(achi), "r"(acli), "r"(rs)
);
if ((acho != reshi) || (aclo != reslo)) {
printf("dshilov error\n");
return -1;
}
return 0;
}

50
tests/tcg/mips/mips64-dsp/extp.c
View File

@ -1,50 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, ach, acl, dsp;
long long result;
ach = 0x05;
acl = 0xB4CB;
dsp = 0x07;
result = 0x000C;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extp %0, $ac1, 0x03\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 14) & 0x01;
if ((dsp != 0) || (result != rt)) {
printf("extp wrong\n");
return -1;
}
ach = 0x05;
acl = 0xB4CB;
dsp = 0x01;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extp %0, $ac1, 0x03\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 14) & 0x01;
if (dsp != 1) {
printf("extp wrong\n");
return -1;
}
return 0;
}

51
tests/tcg/mips/mips64-dsp/extpdp.c
View File

@ -1,51 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, ach, acl, dsp, pos, efi;
long long result;
ach = 0x05;
acl = 0xB4CB;
dsp = 0x07;
result = 0x000C;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extpdp %0, $ac1, 0x03\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl)
);
pos = dsp & 0x3F;
efi = (dsp >> 14) & 0x01;
if ((pos != 3) || (efi != 0) || (result != rt)) {
printf("extpdp wrong\n");
return -1;
}
ach = 0x05;
acl = 0xB4CB;
dsp = 0x01;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extpdp %0, $ac1, 0x03\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl)
);
efi = (dsp >> 14) & 0x01;
if (efi != 1) {
printf("extpdp wrong\n");
return -1;
}
return 0;
}

52
tests/tcg/mips/mips64-dsp/extpdpv.c
View File

@ -1,52 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, rs, ach, acl, dsp, pos, efi;
long long result;
ach = 0x05;
acl = 0xB4CB;
dsp = 0x07;
rs = 0x03;
result = 0x000C;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extpdpv %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl), "r"(rs)
);
pos = dsp & 0x3F;
efi = (dsp >> 14) & 0x01;
if ((pos != 3) || (efi != 0) || (result != rt)) {
printf("extpdpv wrong\n");
return -1;
}
ach = 0x05;
acl = 0xB4CB;
dsp = 0x01;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extpdpv %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl), "r"(rs)
);
efi = (dsp >> 14) & 0x01;
if (efi != 1) {
printf("extpdpv wrong\n");
return -1;
}
return 0;
}

51
tests/tcg/mips/mips64-dsp/extpv.c
View File

@ -1,51 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, ac, ach, acl, dsp;
long long result;
ach = 0x05;
acl = 0xB4CB;
dsp = 0x07;
ac = 0x03;
result = 0x000C;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extpv %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl), "r"(ac)
);
dsp = (dsp >> 14) & 0x01;
if ((dsp != 0) || (result != rt)) {
printf("extpv wrong\n");
return -1;
}
ach = 0x05;
acl = 0xB4CB;
dsp = 0x01;
__asm
("wrdsp %1, 0x01\n\t"
"mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extpv %0, $ac1, %4\n\t"
"rddsp %1\n\t"
: "=r"(rt), "+r"(dsp)
: "r"(ach), "r"(acl), "r"(ac)
);
dsp = (dsp >> 14) & 0x01;
if (dsp != 1) {
printf("extpv wrong\n");
return -1;
}
return 0;
}

53
tests/tcg/mips/mips64-dsp/extr_r_w.c
View File

@ -1,53 +0,0 @@
#include "io.h"
int main(void)
{
long long rt, ach, acl, dsp;
long long result;
ach = 0x05;
acl = 0xB4CB;
result = 0xFFFFFFFFA0001699;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extr_r.w %0, $ac1, 0x03\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 23) & 0x01;
if ((dsp != 1) || (result != rt)) {
printf("1 extr_r.w wrong\n");
return -1;
}
/* Clear dspcontrol */
dsp = 0;
__asm
("wrdsp %0\n\t"
:
: "r"(dsp)
);
ach = 0x01;
acl = 0xB4CB;
result = 0x10000B4D;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extr_r.w %0, $ac1, 0x04\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 23) & 0x01;
if ((dsp != 0) || (result != rt)) {
printf("2 extr_r.w wrong\n");
return -1;
}
return 0;
}

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