mirror of https://github.com/xqemu/xqemu.git
powerpc: Add a virtex5 ml507 refdesign board
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Edgar E. Iglesias
parent
95070372f7
commit
2c50e26efd
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@ -217,9 +217,17 @@ obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
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obj-ppc-y += ppc440.o ppc440_bamboo.o
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# PowerPC E500 boards
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obj-ppc-y += ppce500_mpc8544ds.o
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# PowerPC 440 Xilinx ML507 reference board.
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obj-ppc-y += virtex_ml507.o
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obj-ppc-$(CONFIG_KVM) += kvm_ppc.o
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obj-ppc-$(CONFIG_FDT) += device_tree.o
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# Xilinx PPC peripherals
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obj-ppc-y += xilinx_intc.o
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obj-ppc-y += xilinx_timer.o
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obj-ppc-y += xilinx_uartlite.o
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obj-ppc-y += xilinx_ethlite.o
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obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
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obj-mips-y += mips_addr.o mips_timer.o mips_int.o
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obj-mips-y += vga.o i8259.o
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@ -32,4 +32,6 @@ CONFIG_IDE_MACIO=y
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CONFIG_NE2000_ISA=y
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CONFIG_SOUND=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI01=y
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CONFIG_PFLASH_CFI02=y
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CONFIG_PTIMER=y
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@ -32,4 +32,6 @@ CONFIG_IDE_MACIO=y
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CONFIG_NE2000_ISA=y
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CONFIG_SOUND=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI01=y
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CONFIG_PFLASH_CFI02=y
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CONFIG_PTIMER=y
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@ -32,4 +32,6 @@ CONFIG_IDE_MACIO=y
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CONFIG_NE2000_ISA=y
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CONFIG_SOUND=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI01=y
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CONFIG_PFLASH_CFI02=y
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CONFIG_PTIMER=y
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@ -0,0 +1,278 @@
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/*
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* Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
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*
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* Copyright (c) 2010 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "hw.h"
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#include "pc.h"
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#include "net.h"
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#include "flash.h"
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#include "sysemu.h"
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#include "devices.h"
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#include "boards.h"
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#include "device_tree.h"
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#include "loader.h"
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#include "elf.h"
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#include "qemu-log.h"
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#include "ppc.h"
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#include "ppc4xx.h"
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#include "ppc440.h"
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#include "ppc405.h"
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#include "blockdev.h"
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#include "xilinx.h"
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#define EPAPR_MAGIC (0x45504150)
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#define FLASH_SIZE (16 * 1024 * 1024)
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static struct boot_info
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{
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uint32_t bootstrap_pc;
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uint32_t cmdline;
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uint32_t fdt;
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uint32_t ima_size;
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void *vfdt;
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} boot_info;
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/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
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static void mmubooke_create_initial_mapping(CPUState *env,
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target_ulong va,
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target_phys_addr_t pa)
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{
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ppcemb_tlb_t *tlb = &env->tlb[0].tlbe;
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1 << 31; /* up to 0x80000000 */
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tlb->EPN = va & TARGET_PAGE_MASK;
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tlb->RPN = pa & TARGET_PAGE_MASK;
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tlb->PID = 0;
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tlb = &env->tlb[1].tlbe;
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1 << 31; /* up to 0xffffffff */
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tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->PID = 0;
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}
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static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size,
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int do_init,
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const char *cpu_model,
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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uint32_t sysclk)
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{
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CPUState *env;
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qemu_irq *pic;
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qemu_irq *irqs;
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
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cpu_clk->opaque = env;
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/* Set time-base frequency to sysclk */
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tb_clk->cb = ppc_emb_timers_init(env, sysclk, PPC_INTERRUPT_DECR);
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tb_clk->opaque = env;
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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return env;
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}
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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struct boot_info *bi = env->load_info;
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cpu_reset(env);
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/* Linux Kernel Parameters (passing device tree):
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* r3: pointer to the fdt
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* r4: 0
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* r5: 0
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* r6: epapr magic
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* r7: size of IMA in bytes
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* r8: 0
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* r9: 0
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*/
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env->gpr[1] = (16<<20) - 8;
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/* Provide a device-tree. */
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env->gpr[3] = bi->fdt;
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env->nip = bi->bootstrap_pc;
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/* Create a mapping for the kernel. */
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mmubooke_create_initial_mapping(env, 0, 0);
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env->gpr[6] = tswap32(EPAPR_MAGIC);
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env->gpr[7] = bi->ima_size;
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}
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#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
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static int xilinx_load_device_tree(target_phys_addr_t addr,
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uint32_t ramsize,
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target_phys_addr_t initrd_base,
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target_phys_addr_t initrd_size,
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const char *kernel_cmdline)
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{
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char *path;
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int fdt_size;
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#ifdef CONFIG_FDT
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void *fdt;
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int r;
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/* Try the local "ppc.dtb" override. */
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fdt = load_device_tree("ppc.dtb", &fdt_size);
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if (!fdt) {
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path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (path) {
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fdt = load_device_tree(path, &fdt_size);
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qemu_free(path);
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}
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if (!fdt)
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return 0;
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}
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r = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
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if (r < 0)
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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cpu_physical_memory_write (addr, (void *)fdt, fdt_size);
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#else
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/* We lack libfdt so we cannot manipulate the fdt. Just pass on the blob
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to the kernel. */
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fdt_size = load_image_targphys("ppc.dtb", addr, 0x10000);
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if (fdt_size < 0) {
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path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (path) {
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fdt_size = load_image_targphys(path, addr, 0x10000);
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qemu_free(path);
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}
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}
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if (kernel_cmdline) {
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fprintf(stderr,
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"Warning: missing libfdt, cannot pass cmdline to kernel!\n");
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}
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#endif
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return fdt_size;
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}
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static void virtex_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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DeviceState *dev;
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CPUState *env;
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target_phys_addr_t ram_base = 0;
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DriveInfo *dinfo;
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ram_addr_t phys_ram;
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ram_addr_t phys_flash;
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qemu_irq irq[32], *cpu_irq;
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clk_setup_t clk_setup[7];
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int kernel_size;
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int i;
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/* init CPUs */
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if (cpu_model == NULL) {
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cpu_model = "440-Xilinx";
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}
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memset(clk_setup, 0, sizeof(clk_setup));
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env = ppc440_init_xilinx(&ram_size, 1, cpu_model, &clk_setup[0],
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&clk_setup[1], 400000000);
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qemu_register_reset(main_cpu_reset, env);
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phys_ram = qemu_ram_alloc(NULL, "ram", ram_size);
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cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
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phys_flash = qemu_ram_alloc(NULL, "virtex.flash", FLASH_SIZE);
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dinfo = drive_get(IF_PFLASH, 0, 0);
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pflash_cfi01_register(0xfc000000, phys_flash,
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dinfo ? dinfo->bdrv : NULL, (64 * 1024),
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FLASH_SIZE >> 16,
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1, 0x89, 0x18, 0x0000, 0x0, 1);
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cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
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dev = xilinx_intc_create(0x81800000, cpu_irq[0], 0);
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(dev, i);
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}
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serial_mm_init(0x83e01003ULL, 2, irq[9], 115200, serial_hds[0], 1, 0);
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/* 2 timers at irq 2 @ 62 Mhz. */
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xilinx_timer_create(0x83c00000, irq[3], 2, 62 * 1000000);
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if (kernel_filename) {
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uint64_t entry, low, high;
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uint32_t base32;
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target_phys_addr_t boot_offset;
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/* Boots a kernel elf binary. */
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kernel_size = load_elf(kernel_filename, NULL, NULL,
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&entry, &low, &high, 1, ELF_MACHINE, 0);
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base32 = entry;
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boot_info.bootstrap_pc = entry & 0x00ffffff;
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if (kernel_size < 0) {
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boot_offset = 0x1200000;
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/* If we failed loading ELF's try a raw image. */
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kernel_size = load_image_targphys(kernel_filename,
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boot_offset,
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ram_size);
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boot_info.bootstrap_pc = boot_offset;
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high = boot_info.bootstrap_pc + kernel_size + 8192;
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}
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boot_info.ima_size = kernel_size;
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/* Provide a device-tree. */
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boot_info.fdt = high + (8192 * 2);
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boot_info.fdt &= ~8191;
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xilinx_load_device_tree(boot_info.fdt, ram_size, 0, 0, kernel_cmdline);
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}
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env->load_info = &boot_info;
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}
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static QEMUMachine virtex_machine = {
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.name = "virtex-ml507",
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.desc = "Xilinx Virtex ML507 reference design",
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.init = virtex_init,
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};
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static void virtex_machine_init(void)
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{
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qemu_register_machine(&virtex_machine);
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}
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machine_init(virtex_machine_init);
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@ -702,6 +702,10 @@ struct CPUPPCState {
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/* temporary hack to handle OSI calls (only used if non NULL) */
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int (*osi_call)(struct CPUPPCState *env);
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#if !defined(CONFIG_USER_ONLY)
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void *load_info; /* Holds boot loading state. */
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#endif
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};
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#if !defined(CONFIG_USER_ONLY)
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