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microblaze: avoid "naked" qemu_log 

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2015-11-13 13:24:57 +01:00
parent 79e8ed3597
commit 1d512a65ac
4 changed files with 16 additions and 16 deletions
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2
target-microblaze/helper.c
View File

@ -128,7 +128,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) { switch (cs->exception_index) {
case EXCP_HW_EXCP: case EXCP_HW_EXCP:
if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
qemu_log("Exception raised on system without exceptions!\n"); qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
return; return;
} }

20
target-microblaze/mmu.c
View File

@ -60,7 +60,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
uint32_t t; uint32_t t;
if (newpid & ~0xff) if (newpid & ~0xff)
qemu_log("Illegal rpid=%x\n", newpid); qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
/* Lookup and decode. */ /* Lookup and decode. */
@ -121,7 +121,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
t0 &= 0x3; t0 &= 0x3;
if (tlb_zsel > mmu->c_mmu_zones) { if (tlb_zsel > mmu->c_mmu_zones) {
qemu_log("tlb zone select out of range! %d\n", tlb_zsel); qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel);
t0 = 1; /* Ignore. */ t0 = 1; /* Ignore. */
} }
@ -183,7 +183,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
uint32_t r; uint32_t r;
if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
qemu_log("MMU access on MMU-less system\n"); qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
return 0; return 0;
} }
@ -192,7 +192,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
case MMU_R_TLBLO: case MMU_R_TLBLO:
case MMU_R_TLBHI: case MMU_R_TLBHI:
if (!(env->mmu.c_mmu_tlb_access & 1)) { if (!(env->mmu.c_mmu_tlb_access & 1)) {
qemu_log("Invalid access to MMU reg %d\n", rn); qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
return 0; return 0;
} }
@ -204,7 +204,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
case MMU_R_PID: case MMU_R_PID:
case MMU_R_ZPR: case MMU_R_ZPR:
if (!(env->mmu.c_mmu_tlb_access & 1)) { if (!(env->mmu.c_mmu_tlb_access & 1)) {
qemu_log("Invalid access to MMU reg %d\n", rn); qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
return 0; return 0;
} }
r = env->mmu.regs[rn]; r = env->mmu.regs[rn];
@ -224,7 +224,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn])); D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
qemu_log("MMU access on MMU-less system\n"); qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
return; return;
} }
@ -235,7 +235,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
i = env->mmu.regs[MMU_R_TLBX] & 0xff; i = env->mmu.regs[MMU_R_TLBX] & 0xff;
if (rn == MMU_R_TLBHI) { if (rn == MMU_R_TLBHI) {
if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
qemu_log("invalidating index %x at pc=%x\n", qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n",
i, env->sregs[SR_PC]); i, env->sregs[SR_PC]);
env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
mmu_flush_idx(env, i); mmu_flush_idx(env, i);
@ -246,7 +246,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
break; break;
case MMU_R_ZPR: case MMU_R_ZPR:
if (env->mmu.c_mmu_tlb_access <= 1) { if (env->mmu.c_mmu_tlb_access <= 1) {
qemu_log("Invalid access to MMU reg %d\n", rn); qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
return; return;
} }
@ -259,7 +259,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
break; break;
case MMU_R_PID: case MMU_R_PID:
if (env->mmu.c_mmu_tlb_access <= 1) { if (env->mmu.c_mmu_tlb_access <= 1) {
qemu_log("Invalid access to MMU reg %d\n", rn); qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
return; return;
} }
@ -274,7 +274,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
int hit; int hit;
if (env->mmu.c_mmu_tlb_access <= 1) { if (env->mmu.c_mmu_tlb_access <= 1) {
qemu_log("Invalid access to MMU reg %d\n", rn); qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
return; return;
} }

8
target-microblaze/op_helper.c
View File

@ -55,7 +55,7 @@ void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
int nonblock = ctrl & STREAM_NONBLOCK; int nonblock = ctrl & STREAM_NONBLOCK;
int exception = ctrl & STREAM_EXCEPTION; int exception = ctrl & STREAM_EXCEPTION;
qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n", qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
id, data, id, data,
test ? "t" : "", test ? "t" : "",
nonblock ? "n" : "", nonblock ? "n" : "",
@ -72,7 +72,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
int nonblock = ctrl & STREAM_NONBLOCK; int nonblock = ctrl & STREAM_NONBLOCK;
int exception = ctrl & STREAM_EXCEPTION; int exception = ctrl & STREAM_EXCEPTION;
qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n", qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
id, id,
test ? "t" : "", test ? "t" : "",
nonblock ? "n" : "", nonblock ? "n" : "",
@ -465,8 +465,8 @@ void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
void helper_stackprot(CPUMBState *env, uint32_t addr) void helper_stackprot(CPUMBState *env, uint32_t addr)
{ {
if (addr < env->slr || addr > env->shr) { if (addr < env->slr || addr > env->shr) {
qemu_log("Stack protector violation at %x %x %x\n", qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
addr, env->slr, env->shr); addr, env->slr, env->shr);
env->sregs[SR_EAR] = addr; env->sregs[SR_EAR] = addr;
env->sregs[SR_ESR] = ESR_EC_STACKPROT; env->sregs[SR_ESR] = ESR_EC_STACKPROT;
helper_raise_exception(env, EXCP_HW_EXCP); helper_raise_exception(env, EXCP_HW_EXCP);

2
target-microblaze/translate.c
View File

@ -1516,7 +1516,7 @@ static void dec_null(DisasContext *dc)
t_gen_raise_exception(dc, EXCP_HW_EXCP); t_gen_raise_exception(dc, EXCP_HW_EXCP);
return; return;
} }
qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
dc->abort_at_next_insn = 1; dc->abort_at_next_insn = 1;
} }