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tcg: fix s/compliment/complement/ typos 

Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Emilio G. Cota 2018-03-05 17:13:30 -05:00 committed by Michael Tokarev
parent 5bcf917ee3
commit 1d34982155
3 changed files with 3 additions and 3 deletions
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2
target/i386/translate.c
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@ -113,7 +113,7 @@ typedef struct DisasContext {
int rex_x, rex_b; int rex_x, rex_b;
#endif #endif
int vex_l; /* vex vector length */ int vex_l; /* vex vector length */
int vex_v; /* vex vvvv register, without 1's compliment. */ int vex_v; /* vex vvvv register, without 1's complement. */
int ss32; /* 32 bit stack segment */ int ss32; /* 32 bit stack segment */
CCOp cc_op; /* current CC operation */ CCOp cc_op; /* current CC operation */
bool cc_op_dirty; bool cc_op_dirty;

2
target/m68k/translate.c
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@ -4002,7 +4002,7 @@ DISAS_INSN(bfext_reg)
TCGv shift; TCGv shift;
/* In general, we're going to rotate the field so that it's at the /* In general, we're going to rotate the field so that it's at the
top of the word and then right-shift by the compliment of the top of the word and then right-shift by the complement of the
width to extend the field. */ width to extend the field. */
if (ext & 0x20) { if (ext & 0x20) {
/* Variable width. */ /* Variable width. */

2
tcg/README
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@ -561,7 +561,7 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
* orc_vec v0, v1, v2 * orc_vec v0, v1, v2
* not_vec v0, v1 * not_vec v0, v1
Similarly, logical operations with and without compliment. Similarly, logical operations with and without complement.
Note that VECE is unused. Note that VECE is unused.
* shli_vec v0, v1, i2 * shli_vec v0, v1, i2