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target-mips: Use clz opcode 

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2016-11-16 11:11:54 +01:00
parent 5318420c62
commit 1a0196c5c7
3 changed files with 16 additions and 36 deletions
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7
target/mips/helper.h
View File

@ -20,13 +20,6 @@ DEF_HELPER_4(scd, tl, env, tl, tl, int)
#endif #endif
#endif #endif
DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, tl, tl)
#ifdef TARGET_MIPS64
DEF_HELPER_FLAGS_1(dclo, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(dclz, TCG_CALL_NO_RWG_SE, tl, tl)
#endif
DEF_HELPER_3(muls, tl, env, tl, tl) DEF_HELPER_3(muls, tl, env, tl, tl)
DEF_HELPER_3(mulsu, tl, env, tl, tl) DEF_HELPER_3(mulsu, tl, env, tl, tl)
DEF_HELPER_3(macc, tl, env, tl, tl) DEF_HELPER_3(macc, tl, env, tl, tl)

22
target/mips/op_helper.c
View File

@ -103,28 +103,6 @@ HELPER_ST(sd, stq, uint64_t)
#endif #endif
#undef HELPER_ST #undef HELPER_ST
target_ulong helper_clo (target_ulong arg1)
{
return clo32(arg1);
}
target_ulong helper_clz (target_ulong arg1)
{
return clz32(arg1);
}
#if defined(TARGET_MIPS64)
target_ulong helper_dclo (target_ulong arg1)
{
return clo64(arg1);
}
target_ulong helper_dclz (target_ulong arg1)
{
return clz64(arg1);
}
#endif /* TARGET_MIPS64 */
/* 64 bits arithmetic for 32 bits hosts */ /* 64 bits arithmetic for 32 bits hosts */
static inline uint64_t get_HILO(CPUMIPSState *env) static inline uint64_t get_HILO(CPUMIPSState *env)
{ {

23
target/mips/translate.c
View File

@ -3626,29 +3626,38 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
/* Treat as NOP. */ /* Treat as NOP. */
return; return;
} }
t0 = tcg_temp_new(); t0 = cpu_gpr[rd];
gen_load_gpr(t0, rs); gen_load_gpr(t0, rs);
switch (opc) { switch (opc) {
case OPC_CLO: case OPC_CLO:
case R6_OPC_CLO: case R6_OPC_CLO:
gen_helper_clo(cpu_gpr[rd], t0); #if defined(TARGET_MIPS64)
case OPC_DCLO:
case R6_OPC_DCLO:
#endif
tcg_gen_not_tl(t0, t0);
break; break;
}
switch (opc) {
case OPC_CLO:
case R6_OPC_CLO:
case OPC_CLZ: case OPC_CLZ:
case R6_OPC_CLZ: case R6_OPC_CLZ:
gen_helper_clz(cpu_gpr[rd], t0); tcg_gen_ext32u_tl(t0, t0);
tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS);
tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DCLO: case OPC_DCLO:
case R6_OPC_DCLO: case R6_OPC_DCLO:
gen_helper_dclo(cpu_gpr[rd], t0);
break;
case OPC_DCLZ: case OPC_DCLZ:
case R6_OPC_DCLZ: case R6_OPC_DCLZ:
gen_helper_dclz(cpu_gpr[rd], t0); tcg_gen_clzi_i64(t0, t0, 64);
break; break;
#endif #endif
} }
tcg_temp_free(t0);
} }
/* Godson integer instructions */ /* Godson integer instructions */