mirror of https://github.com/xqemu/xqemu.git
debug fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@542 c046a42c-6fe2-441c-8c8c-71466251a162
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parent
4487d0ac49
commit
16d17fdb8e
26
hw/dma.c
26
hw/dma.c
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@ -25,8 +25,8 @@
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#include <stdlib.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <inttypes.h>
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#include "vl.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "vl.h"
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#define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#ifdef DEBUG_DMA
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#ifdef DEBUG_DMA
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@ -79,7 +79,7 @@ enum {
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};
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};
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static void write_page (struct CPUX86State *env, uint32_t nport, uint32_t data)
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static void write_page (CPUState *env, uint32_t nport, uint32_t data)
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{
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{
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int ichan;
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int ichan;
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int ncont;
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int ncont;
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@ -114,7 +114,7 @@ static inline int getff (int ncont)
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return ff;
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return ff;
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}
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}
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static uint32_t read_chan (struct CPUX86State *env, uint32_t nport)
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static uint32_t read_chan (CPUState *env, uint32_t nport)
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{
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{
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int ff;
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int ff;
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int ncont, ichan, nreg;
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int ncont, ichan, nreg;
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@ -160,17 +160,17 @@ static void write_chan (uint32_t nport, int size, uint32_t data)
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}
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}
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}
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}
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}
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}
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static void write_chanb (struct CPUX86State *env, uint32_t nport, uint32_t data)
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static void write_chanb (CPUState *env, uint32_t nport, uint32_t data)
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{
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{
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write_chan (nport, 1, data);
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write_chan (nport, 1, data);
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}
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}
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static void write_chanw (struct CPUX86State *env, uint32_t nport, uint32_t data)
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static void write_chanw (CPUState *env, uint32_t nport, uint32_t data)
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{
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{
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write_chan (nport, 2, data);
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write_chan (nport, 2, data);
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}
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}
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static void write_cont (struct CPUX86State *env, uint32_t nport, uint32_t data)
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static void write_cont (CPUState *env, uint32_t nport, uint32_t data)
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{
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{
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int iport, ichan, ncont;
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int iport, ichan, ncont;
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struct dma_cont *d;
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struct dma_cont *d;
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@ -215,17 +215,17 @@ static void write_cont (struct CPUX86State *env, uint32_t nport, uint32_t data)
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case 0xb: /* mode */
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case 0xb: /* mode */
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{
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{
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#ifdef DMA_DEBUG
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ichan = data & 3;
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#ifdef DEBUG_DMA
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int op;
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int op;
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int ai;
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int ai;
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int dir;
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int dir;
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int opmode;
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int opmode;
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ichan = val & 3;
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op = (data >> 2) & 3;
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op = (val >> 2) & 3;
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ai = (data >> 4) & 1;
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ai = (val >> 4) & 1;
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dir = (data >> 5) & 1;
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dir = (val >> 5) & 1;
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opmode = (data >> 6) & 3;
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opmode = (val >> 6) & 3;
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linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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ichan, op, ai, dir, opmode);
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ichan, op, ai, dir, opmode);
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@ -259,7 +259,7 @@ static void write_cont (struct CPUX86State *env, uint32_t nport, uint32_t data)
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goto error;
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goto error;
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}
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}
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#ifdef DMA_DEBUG
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#ifdef DEBUG_DMA
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if (0xc != iport) {
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if (0xc != iport) {
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linfo ("nport %#06x, ncont %d, ichan % 2d, val %#06x\n",
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linfo ("nport %#06x, ncont %d, ichan % 2d, val %#06x\n",
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nport, d != dma_controllers, ichan, data);
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nport, d != dma_controllers, ichan, data);
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