From b817772a2521defba513b64b1d08238f24c50657 Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Thu, 24 Sep 2015 13:52:47 +0530 Subject: [PATCH 01/21] spapr: Allocate HTAB from machine init Allocate HTAB from ppc_spapr_init() so that we can abort the guest if requested HTAB size is't allocated by the host. However retain the htab reset call in spapr_reset_htab() so that HTAB gets reset (and not allocated) during machine reset. Signed-off-by: Bharata B Rao Signed-off-by: David Gibson --- hw/ppc/spapr.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 3852ad1967..998a77bca2 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -979,7 +979,7 @@ static void emulate_spapr_hypercall(PowerPCCPU *cpu) #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) -static void spapr_reset_htab(sPAPRMachineState *spapr) +static void spapr_alloc_htab(sPAPRMachineState *spapr) { long shift; int index; @@ -994,18 +994,37 @@ static void spapr_reset_htab(sPAPRMachineState *spapr) /* Kernel handles htab, we don't need to allocate one */ spapr->htab_shift = shift; kvmppc_kern_htab = true; + } else { + /* Allocate htab */ + spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); + /* And clear it */ + memset(spapr->htab, 0, HTAB_SIZE(spapr)); + + for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { + DIRTY_HPTE(HPTE(spapr->htab, index)); + } + } +} + +/* + * Clear HTAB entries during reset. + * + * If host kernel has allocated HTAB, KVM_PPC_ALLOCATE_HTAB ioctl is + * used to clear HTAB. Otherwise QEMU-allocated HTAB is cleared manually. + */ +static void spapr_reset_htab(sPAPRMachineState *spapr) +{ + long shift; + int index; + + shift = kvmppc_reset_htab(spapr->htab_shift); + if (shift > 0) { /* Tell readers to update their file descriptor */ if (spapr->htab_fd >= 0) { spapr->htab_fd_stale = true; } } else { - if (!spapr->htab) { - /* Allocate an htab if we don't yet have one */ - spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); - } - - /* And clear it */ memset(spapr->htab, 0, HTAB_SIZE(spapr)); for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { @@ -1710,6 +1729,7 @@ static void ppc_spapr_init(MachineState *machine) } spapr->htab_shift++; } + spapr_alloc_htab(spapr); /* Set up Interrupt Controller before we create the VCPUs */ spapr->icp = xics_system_init(machine, From 7735fedaf490cf9213cd8d487272b69a4987c851 Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Thu, 24 Sep 2015 13:52:48 +0530 Subject: [PATCH 02/21] spapr: Abort when HTAB of requested size isn't allocated Terminate the guest when HTAB of requested size isn't allocated by the host. When memory hotplug is attempted on a guest that has booted with less than requested HTAB size, the guest kernel will not be able to gracefully fail the hotplug request. This patch will ensure that we never end up in a situation where memory hotplug fails due to less than requested HTAB size. Signed-off-by: Bharata B Rao Signed-off-by: David Gibson --- hw/ppc/spapr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 998a77bca2..f90f59283d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -992,6 +992,10 @@ static void spapr_alloc_htab(sPAPRMachineState *spapr) if (shift > 0) { /* Kernel handles htab, we don't need to allocate one */ + if (shift != spapr->htab_shift) { + error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); + } + spapr->htab_shift = shift; kvmppc_kern_htab = true; } else { @@ -1020,6 +1024,10 @@ static void spapr_reset_htab(sPAPRMachineState *spapr) shift = kvmppc_reset_htab(spapr->htab_shift); if (shift > 0) { + if (shift != spapr->htab_shift) { + error_setg(&error_abort, "Requested HTAB allocation failed during reset"); + } + /* Tell readers to update their file descriptor */ if (spapr->htab_fd >= 0) { spapr->htab_fd_stale = true; From fd5da5c47264a57c7d01507eaf50bf3d288ba8a4 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Thu, 1 Oct 2015 15:30:07 +0200 Subject: [PATCH 03/21] spapr: Add "slb-size" property to CPU device tree nodes According to a commit message in the Linux kernel (see here https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=b60c31d85a2a for example), the name of the property that carries the information about the number of SLB entries should be called "slb-size", and not "ibm,slb-size". The Linux kernel can deal with both names, but to be on the safe side we should support the official name, too. [Now that LoPAPR is public, the relevant requirement can be found in section C.6.1.8 --dwg] Signed-off-by: Thomas Huth Signed-off-by: David Gibson --- hw/ppc/spapr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f90f59283d..3ba1e90aee 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -625,6 +625,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); + _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); From f93caaac36ec3b030184055596cb56f64d0de988 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 24 Sep 2015 09:56:44 +1000 Subject: [PATCH 04/21] spapr_pci: Allow PCI host bridge DMA window to be configured At present the PCI host bridge (PHB) for the pseries machine type has a fixed DMA window from 0..1GB (in PCI address space) which is mapped to real memory via the PAPR paravirtualized IOMMU. For better support of VFIO devices, we're going to want to allow for different configurations of the DMA window. Eventually we'll want to allow the guest itself to reconfigure the window via the PAPR dynamic DMA window interface, but as a preliminary this patch allows the user to reconfigure the window with new properties on the PHB device. Signed-off-by: David Gibson Reviewed-by: Thomas Huth Reviewed-by: Laurent Vivier --- hw/ppc/spapr_pci.c | 7 +++++-- include/hw/pci-host/spapr.h | 3 +-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 617b7f3fdd..cb7c351474 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1387,7 +1387,7 @@ static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) sPAPRTCETable *tcet; uint32_t nb_table; - nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; + nb_table = sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT; tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); if (!tcet) { @@ -1397,7 +1397,7 @@ static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) } /* Register default 32bit DMA window */ - memory_region_add_subregion(&sphb->iommu_root, 0, + memory_region_add_subregion(&sphb->iommu_root, sphb->dma_win_addr, spapr_tce_get_iommu(tcet)); } @@ -1430,6 +1430,9 @@ static Property spapr_phb_properties[] = { SPAPR_PCI_IO_WIN_SIZE), DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, true), + /* Default DMA window is 0..1GB */ + DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0), + DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 5322b560eb..7de5e029b1 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -78,6 +78,7 @@ struct sPAPRPHBState { MemoryRegion memwindow, iowindow, msiwindow; uint32_t dma_liobn; + hwaddr dma_win_addr, dma_win_size; AddressSpace iommu_as; MemoryRegion iommu_root; @@ -115,8 +116,6 @@ struct sPAPRPHBVFIOState { #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL -#define SPAPR_PCI_DMA32_SIZE 0x40000000 - static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) { sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); From 6a81dd172cd5d03fce593741629cb4c78fff10cb Mon Sep 17 00:00:00 2001 From: David Gibson Date: Wed, 30 Sep 2015 13:42:55 +1000 Subject: [PATCH 05/21] spapr_iommu: Rename vfio_accel parameter The vfio_accel parameter used when creating a new TCE table (guest IOMMU context) has a confusing name. What it really means is whether we need the TCE table created to be able to support VFIO devices. VFIO is relevant, because when available we use in-kernel acceleration of the TCE table, but that may not work with VFIO devices because updates to the table are handled in kernel, bypass qemu and so don't hit qemu's infrastructure for keeping the VFIO host IOMMU state in sync with the guest IOMMU state. Rename the parameter to "need_vfio" throughout. This is a cosmetic change, with no impact on the logic. Signed-off-by: David Gibson Reviewed-by: Laurent Vivier --- hw/ppc/spapr_iommu.c | 6 +++--- include/hw/ppc/spapr.h | 4 ++-- target-ppc/kvm.c | 4 ++-- target-ppc/kvm_ppc.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index f61504e0c5..5166cde422 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -146,7 +146,7 @@ static int spapr_tce_table_realize(DeviceState *dev) tcet->table = kvmppc_create_spapr_tce(tcet->liobn, window_size, &tcet->fd, - tcet->vfio_accel); + tcet->need_vfio); } if (!tcet->table) { @@ -172,7 +172,7 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, uint64_t bus_offset, uint32_t page_shift, uint32_t nb_table, - bool vfio_accel) + bool need_vfio) { sPAPRTCETable *tcet; char tmp[64]; @@ -192,7 +192,7 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, tcet->bus_offset = bus_offset; tcet->page_shift = page_shift; tcet->nb_table = nb_table; - tcet->vfio_accel = vfio_accel; + tcet->need_vfio = need_vfio; snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn); object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 56c5b0b2b8..27d65d5f1d 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -563,7 +563,7 @@ struct sPAPRTCETable { uint32_t page_shift; uint64_t *table; bool bypass; - bool vfio_accel; + bool need_vfio; int fd; MemoryRegion iommu; struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ @@ -588,7 +588,7 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, uint64_t bus_offset, uint32_t page_shift, uint32_t nb_table, - bool vfio_accel); + bool need_vfio); MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); int spapr_dma_dt(void *fdt, int node_off, const char *propname, uint32_t liobn, uint64_t window, uint32_t size); diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 38aa927eb0..3db9d2b31d 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -2070,7 +2070,7 @@ bool kvmppc_spapr_use_multitce(void) } void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd, - bool vfio_accel) + bool need_vfio) { struct kvm_create_spapr_tce args = { .liobn = liobn, @@ -2084,7 +2084,7 @@ void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd, * destroying the table, which the upper layers -will- do */ *pfd = -1; - if (!cap_spapr_tce || (vfio_accel && !cap_spapr_vfio)) { + if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { return NULL; } diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h index 470f6d62f7..309cbe0df1 100644 --- a/target-ppc/kvm_ppc.h +++ b/target-ppc/kvm_ppc.h @@ -36,7 +36,7 @@ int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu); off_t kvmppc_alloc_rma(void **rma); bool kvmppc_spapr_use_multitce(void); void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd, - bool vfio_accel); + bool need_vfio); int kvmppc_remove_spapr_tce(void *table, int pfd, uint32_t window_size); int kvmppc_reset_htab(int shift_hint); uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift); From c10325d6f9af84444120d8a6d1d59f41a282ae1b Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 1 Oct 2015 10:46:10 +1000 Subject: [PATCH 06/21] spapr_iommu: Provide a function to switch a TCE table to allowing VFIO Because of the way non-VFIO guest IOMMU operations are KVM accelerated, not all TCE tables (guest IOMMU contexts) can support VFIO devices. Currently, this is decided at creation time. To support hotplug of VFIO devices, we need to allow a TCE table which previously didn't allow VFIO devices to be switched so that it can. This patch adds an spapr_tce_set_need_vfio() function to do this, by reallocating the table in userspace if necessary. Currently this doesn't allow the KVM acceleration to be re-enabled if all the VFIO devices are removed. That's an optimization for another time. Signed-off-by: David Gibson Reviewed-by: Laurent Vivier --- hw/ppc/spapr_iommu.c | 32 ++++++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 2 ++ 2 files changed, 34 insertions(+) diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 5166cde422..ed28565d8c 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -168,6 +168,38 @@ static int spapr_tce_table_realize(DeviceState *dev) return 0; } +void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio) +{ + size_t table_size = tcet->nb_table * sizeof(uint64_t); + void *newtable; + + if (need_vfio == tcet->need_vfio) { + /* Nothing to do */ + return; + } + + if (!need_vfio) { + /* FIXME: We don't support transition back to KVM accelerated + * TCEs yet */ + return; + } + + tcet->need_vfio = true; + + if (tcet->fd < 0) { + /* Table is already in userspace, nothing to be do */ + return; + } + + newtable = g_malloc(table_size); + memcpy(newtable, tcet->table, table_size); + + kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table); + + tcet->fd = -1; + tcet->table = newtable; +} + sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, uint64_t bus_offset, uint32_t page_shift, diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 27d65d5f1d..5baa90683b 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -589,6 +589,8 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, uint32_t page_shift, uint32_t nb_table, bool need_vfio); +void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); + MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); int spapr_dma_dt(void *fdt, int node_off, const char *propname, uint32_t liobn, uint64_t window, uint32_t size); From 185181f8835b1b68409ac4381688eafdca0172cc Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 24 Sep 2015 10:34:23 +1000 Subject: [PATCH 07/21] spapr_pci: Allow VFIO devices to work on the normal PCI host bridge The core VFIO infrastructure more or less allows VFIO devices to work on any normal guest PCI host bridge (PHB) without extra logic. However, the "spapr-pci-host-bridge" device (as opposed to the special "spapr-pci-vfio-host-bridge" device) breaks this by using a partially KVM accelerated implementation of the guest kernel IOMMU which won't work with VFIO devices, without additional kernel support. This patch allows VFIO devices to work on the spapr-pci-host-bridge, by having it switch off KVM TCE acceleration when a VFIO device is added to the PHB (either on startup, or by hotplug). Signed-off-by: David Gibson Reviewed-by: Thomas Huth Reviewed-by: Laurent Vivier --- hw/ppc/spapr_pci.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index cb7c351474..55fa8db9e2 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1083,6 +1083,12 @@ static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, void *fdt = NULL; int fdt_start_offset = 0, fdt_size; + if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { + sPAPRTCETable *tcet = spapr_tce_find_by_liobn(phb->dma_liobn); + + spapr_tce_set_need_vfio(tcet, true); + } + if (dev->hotplugged) { fdt = create_device_tree(&fdt_size); fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); From a23dec105c0faed7b9cba5d07d92df63a04dbb2e Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Thu, 8 Oct 2015 21:35:13 +0200 Subject: [PATCH 08/21] hw/scsi/spapr_vscsi: Remove superfluous memset g_malloc0 already clears the memory, so no need for the additional memset here. Cc: Paolo Bonzini Cc: David Gibson Cc: Alexander Graf Signed-off-by: Thomas Huth Reviewed-by: Eric Blake Signed-off-by: David Gibson --- hw/scsi/spapr_vscsi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c index 891424fae9..f4f5140a4a 100644 --- a/hw/scsi/spapr_vscsi.c +++ b/hw/scsi/spapr_vscsi.c @@ -750,7 +750,6 @@ static void vscsi_report_luns(VSCSIState *s, vscsi_req *req) len = n+8; resp_data = g_malloc0(len); - memset(resp_data, 0, len); stl_be_p(resp_data, n); i = found_lun0 ? 8 : 16; QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { From aa4bb58752310e7906683a2ac99566222c1e7228 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 22 Oct 2015 18:30:58 +1100 Subject: [PATCH 09/21] ppc: Add mmu_model defines for arch 2.03 and 2.07 This removes unused POWERPC_MMU_2_06a/POWERPC_MMU_2_06d. This replaces POWERPC_MMU_64B with POWERPC_MMU_2_03 for POWER5+ to be more explicit about the version of the PowerISA supported. This defines POWERPC_MMU_2_07 and uses it for the POWER8 CPU family. This will not have an immediate effect now but it will in the following patch. This should cause no behavioural change. Signed-off-by: Benjamin Herrenschmidt [aik: rebased, changed commit log] Signed-off-by: Alexey Kardashevskiy Signed-off-by: David Gibson --- target-ppc/cpu.h | 10 +++++----- target-ppc/kvm.c | 8 +++++--- target-ppc/mmu_helper.c | 16 ++++++++-------- target-ppc/translate.c | 4 ++-- target-ppc/translate_init.c | 4 ++-- 5 files changed, 22 insertions(+), 20 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 98ce5a7ab0..69d8cf6bd2 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -117,14 +117,14 @@ enum powerpc_mmu_t { #define POWERPC_MMU_AMR 0x00040000 /* 64 bits PowerPC MMU */ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, + /* Architecture 2.03 and later (has LPCR) */ + POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments) */ - POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments or AMR) */ - POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003, + /* Architecture 2.07 variant */ + POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG + | POWERPC_MMU_AMR | 0x00000004, #endif /* defined(TARGET_PPC64) */ }; diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 3db9d2b31d..b4af75df68 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -259,7 +259,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, info->flags |= KVM_PPC_1T_SEGMENTS; } - if (env->mmu_model == POWERPC_MMU_2_06) { + if (env->mmu_model == POWERPC_MMU_2_06 || + env->mmu_model == POWERPC_MMU_2_07) { info->slb_size = 32; } else { info->slb_size = 64; @@ -272,8 +273,9 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, info->sps[i].enc[0].pte_enc = 0; i++; - /* 64K on MMU 2.06 */ - if (env->mmu_model == POWERPC_MMU_2_06) { + /* 64K on MMU 2.06 and later */ + if (env->mmu_model == POWERPC_MMU_2_06 || + env->mmu_model == POWERPC_MMU_2_07) { info->sps[i].page_shift = 16; info->sps[i].slb_enc = 0x110; info->sps[i].enc[0].page_shift = 16; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 527c6adca3..e52d0e56c2 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1293,9 +1293,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: dump_slb(f, cpu_fprintf, env); break; #endif @@ -1433,9 +1433,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) switch (env->mmu_model) { #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: return ppc_hash64_get_phys_page_debug(env, addr); #endif @@ -1937,9 +1937,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_601: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: #endif /* defined(TARGET_PPC64) */ tlb_flush(CPU(cpu), 1); break; @@ -2011,9 +2011,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c2bc1a7ec6..453509a425 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11327,9 +11327,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: #endif cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b54147350d..2adbb6338d 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8019,7 +8019,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_64B; + pcc->mmu_model = POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif @@ -8243,7 +8243,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_2_06; + pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif From 90da0d5a703839c8db9f37355107955df043b654 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 22 Oct 2015 18:30:59 +1100 Subject: [PATCH 10/21] ppc/spapr: Add "ibm,pa-features" property to the device-tree LoPAPR defines a "ibm,pa-features" per-CPU device tree property which describes extended features of the Processor Architecture. This adds the property to the device tree. At the moment this is the copy of what pHyp advertises except "I=1 (cache inhibited) Large Pages" which is enabled for TCG and disabled when running under HV KVM host with 4K system page size. Signed-off-by: Benjamin Herrenschmidt [aik: rebased, changed commit log, moved ci_large_pages initialization, renamed pa_features arrays] Signed-off-by: Alexey Kardashevskiy Signed-off-by: David Gibson --- hw/ppc/spapr.c | 31 +++++++++++++++++++++++++++++++ target-ppc/cpu.h | 1 + target-ppc/kvm.c | 7 +++++++ target-ppc/translate_init.c | 1 + 4 files changed, 40 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 3ba1e90aee..e1202cec9f 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -597,6 +597,24 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, uint32_t vcpus_per_socket = smp_threads * smp_cores; uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; + /* Note: we keep CI large pages off for now because a 64K capable guest + * provisioned with large pages might otherwise try to map a qemu + * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages + * even if that qemu runs on a 4k host. + * + * We can later add this bit back when we are confident this is not + * an issue (!HV KVM or 64K host) + */ + uint8_t pa_features_206[] = { 6, 0, + 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; + uint8_t pa_features_207[] = { 24, 0, + 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; + uint8_t *pa_features; + size_t pa_size; + _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); @@ -663,6 +681,19 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, page_sizes_prop, page_sizes_prop_size))); } + /* Do the ibm,pa-features property, adjust it for ci-large-pages */ + if (env->mmu_model == POWERPC_MMU_2_06) { + pa_features = pa_features_206; + pa_size = sizeof(pa_features_206); + } else /* env->mmu_model == POWERPC_MMU_2_07 */ { + pa_features = pa_features_207; + pa_size = sizeof(pa_features_207); + } + if (env->ci_large_pages) { + pa_features[3] |= 0x20; + } + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", cs->cpu_index / vcpus_per_socket))); diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 69d8cf6bd2..b34aed6a19 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1073,6 +1073,7 @@ struct CPUPPCState { uint64_t insns_flags2; #if defined(TARGET_PPC64) struct ppc_segment_page_sizes sps; + bool ci_large_pages; #endif #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index b4af75df68..ac70f0897b 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -414,6 +414,13 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) /* Convert to QEMU form */ memset(&env->sps, 0, sizeof(env->sps)); + /* If we have HV KVM, we need to forbid CI large pages if our + * host page size is smaller than 64K. + */ + if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) { + env->ci_large_pages = getpagesize() >= 0x10000; + } + /* * XXX This loop should be an entry wide AND of the capabilities that * the selected CPU has with the capabilities that KVM supports. diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 2adbb6338d..4934c80b8f 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7864,6 +7864,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) gen_spr_book3s_ids(env); gen_spr_amr(env); gen_spr_book3s_purr(env); + env->ci_large_pages = true; break; default: g_assert_not_reached(); From 32f3a8992ea28a194678832eec1e1ffc09cbb7b1 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:03 +0200 Subject: [PATCH 11/21] adb: add to input category The Apple Desktop Bus is used to connect a keyboard and a mouse, so add it to the input category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/input/adb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/input/adb.c b/hw/input/adb.c index a18eea2652..09eead96b6 100644 --- a/hw/input/adb.c +++ b/hw/input/adb.c @@ -362,6 +362,7 @@ static void adb_kbd_class_init(ObjectClass *oc, void *data) akc->parent_realize = dc->realize; dc->realize = adb_kbd_realizefn; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); adc->devreq = adb_kbd_request; dc->reset = adb_kbd_reset; @@ -566,6 +567,7 @@ static void adb_mouse_class_init(ObjectClass *oc, void *data) amc->parent_realize = dc->realize; dc->realize = adb_mouse_realizefn; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); adc->devreq = adb_mouse_request; dc->reset = adb_mouse_reset; From 74623e7369b175fa324421f4c0047d06da3baafc Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:04 +0200 Subject: [PATCH 12/21] cmd646: add to storage category cmd646 is an IDE controller, so add it to the storage category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/ide/cmd646.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index 66fb9d96d5..27f3da21a7 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -417,6 +417,7 @@ static void cmd646_ide_class_init(ObjectClass *klass, void *data) k->config_read = cmd646_pci_config_read; k->config_write = cmd646_pci_config_write; dc->props = cmd646_ide_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo cmd646_ide_info = { From f8d4c07c7807d0f7be02f42d2ee849d2eea4141e Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:05 +0200 Subject: [PATCH 13/21] escc: add to input category ESCC is a serial port controller, so add it to the input category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/char/escc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/char/escc.c b/hw/char/escc.c index ba653efd68..9816154206 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -1035,6 +1035,7 @@ static void escc_class_init(ObjectClass *klass, void *data) dc->reset = escc_reset; dc->vmsd = &vmstate_escc; dc->props = escc_properties; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } static const TypeInfo escc_info = { From e16244355f8d5efc94df965b1f6a5a0b6c50a2f2 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:06 +0200 Subject: [PATCH 14/21] grackle: add to bridge category Grackle is the PCI host controller of oldworld powermac, so add it to the bridge category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/pci-host/grackle.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c index bfe707a1a1..ea31b72e7c 100644 --- a/hw/pci-host/grackle.c +++ b/hw/pci-host/grackle.c @@ -146,8 +146,10 @@ static const TypeInfo grackle_pci_info = { static void pci_grackle_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->init = pci_grackle_init_device; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo grackle_pci_host_info = { From 599d7326c35d323c0a2cf18ebf65c613979e7f65 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:07 +0200 Subject: [PATCH 15/21] cuda: add to bridge category Cuda is a bridge between PowerMac system bus and the ADB controller, real-time clock, pram and the power management unit. So add it to the bridge category. Signed-off-by: Laurent Vivier Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 5d7043e99c..0fd75b376f 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -738,6 +738,7 @@ static void cuda_class_init(ObjectClass *oc, void *data) dc->reset = cuda_reset; dc->vmsd = &vmstate_cuda; dc->props = cuda_properties; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo cuda_type_info = { From 3469d9bce86d2e387777addb25ed8b80b7e9d2a1 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:08 +0200 Subject: [PATCH 16/21] macio-ide: add to storage category macio-ide is an IDE controller, so add it to the storage category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Reviewed-by: John Snow Signed-off-by: David Gibson --- hw/ide/macio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 66ac2baa94..893c9b9bae 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -590,6 +590,7 @@ static void macio_ide_class_init(ObjectClass *oc, void *data) dc->realize = macio_ide_realizefn; dc->reset = macio_ide_reset; dc->vmsd = &vmstate_pmac; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo macio_ide_type_info = { From 1d16f86a433a323691dcfd0f71acdc7592c114fc Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:09 +0200 Subject: [PATCH 17/21] uninorth: add to bridge category Uninorth is the mac99 PCI host controller, so add it to the bridge category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/pci-host/uninorth.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c index f0144eb7b0..215b64ffed 100644 --- a/hw/pci-host/uninorth.c +++ b/hw/pci-host/uninorth.c @@ -446,8 +446,10 @@ static const TypeInfo unin_internal_pci_host_info = { static void pci_unin_main_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); sbc->init = pci_unin_main_init_device; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo pci_unin_main_info = { @@ -460,8 +462,10 @@ static const TypeInfo pci_unin_main_info = { static void pci_u3_agp_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); sbc->init = pci_u3_agp_init_device; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo pci_u3_agp_info = { @@ -474,8 +478,10 @@ static const TypeInfo pci_u3_agp_info = { static void pci_unin_agp_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); sbc->init = pci_unin_agp_init_device; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo pci_unin_agp_info = { @@ -488,8 +494,10 @@ static const TypeInfo pci_unin_agp_info = { static void pci_unin_internal_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); sbc->init = pci_unin_internal_init_device; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo pci_unin_internal_info = { From f9f2a9f26f74b4572c51e74be7fd97fa34c920d3 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:10 +0200 Subject: [PATCH 18/21] macio: add to bridge category macio is a bridge between the PCI bus and the Mac nvram, IDE controller and PIC, so add it to the bridge category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/misc/macio/macio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index c661f86c21..adb990e565 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -393,6 +393,7 @@ static void macio_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_APPLE; k->class_id = PCI_CLASS_OTHERS << 8; dc->props = macio_properties; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } static const TypeInfo macio_oldworld_type_info = { From 175fe9e7c886263258602262c341c472bc64be42 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:11 +0200 Subject: [PATCH 19/21] macio-nvram: add to misc category The macio nvram is a non volatile RAM, so add it the misc category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/nvram/mac_nvram.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c index d35f8a3121..9f165664c6 100644 --- a/hw/nvram/mac_nvram.c +++ b/hw/nvram/mac_nvram.c @@ -123,6 +123,7 @@ static void macio_nvram_class_init(ObjectClass *oc, void *data) dc->reset = macio_nvram_reset; dc->vmsd = &vmstate_macio_nvram; dc->props = macio_nvram_properties; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo macio_nvram_type_info = { From 29f8dd66e89d59f66105af9065c10e21f85cc653 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sat, 26 Sep 2015 18:22:12 +0200 Subject: [PATCH 20/21] openpic: add to misc category openpic is a programmable interrupt controller, so add it to the misc category. Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/intc/openpic.c | 1 + hw/intc/openpic_kvm.c | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 14ab0e31b8..bfcf155356 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -1643,6 +1643,7 @@ static void openpic_class_init(ObjectClass *oc, void *data) dc->props = openpic_properties; dc->reset = openpic_reset; dc->vmsd = &vmstate_openpic; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo openpic_info = { diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c index f7cac585a9..649f476ac8 100644 --- a/hw/intc/openpic_kvm.c +++ b/hw/intc/openpic_kvm.c @@ -275,6 +275,7 @@ static void kvm_openpic_class_init(ObjectClass *oc, void *data) dc->realize = kvm_openpic_realize; dc->props = kvm_openpic_properties; dc->reset = kvm_openpic_reset; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo kvm_openpic_info = { From 659f7f65561e78d720986d61f3112c54a97b2b96 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 16 Oct 2015 15:16:11 +0200 Subject: [PATCH 21/21] prep: do not use CPU_LOG_IOPORT, convert to tracepoints These messages are disabled by default; a perfect usecase for tracepoints. Convert them over. Signed-off-by: Paolo Bonzini Signed-off-by: David Gibson --- hw/ppc/prep.c | 30 +++--------------------------- trace-events | 4 ++++ 2 files changed, 7 insertions(+), 27 deletions(-) diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index d95222bd7d..5ad28f75cf 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -42,11 +42,9 @@ #include "sysemu/arch_init.h" #include "sysemu/qtest.h" #include "exec/address-spaces.h" +#include "trace.h" #include "elf.h" -//#define HARD_DEBUG_PPC_IO -//#define DEBUG_PPC_IO - /* SMP is not enabled, for now */ #define MAX_CPUS 1 @@ -57,26 +55,6 @@ #define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 -#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) -#define DEBUG_PPC_IO -#endif - -#if defined (HARD_DEBUG_PPC_IO) -#define PPC_IO_DPRINTF(fmt, ...) \ -do { \ - if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ - qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ - } else { \ - printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ - } \ -} while (0) -#elif defined (DEBUG_PPC_IO) -#define PPC_IO_DPRINTF(fmt, ...) \ -qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) -#else -#define PPC_IO_DPRINTF(fmt, ...) do { } while (0) -#endif - /* Constants for devices init */ static const int ide_iobase[2] = { 0x1f0, 0x170 }; static const int ide_iobase2[2] = { 0x3f6, 0x376 }; @@ -199,8 +177,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) { sysctrl_t *sysctrl = opaque; - PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", - addr - PPC_IO_BASE, val); + trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); switch (addr) { case 0x0092: /* Special port 92 */ @@ -327,8 +304,7 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); break; } - PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", - addr - PPC_IO_BASE, retval); + trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); return retval; } diff --git a/trace-events b/trace-events index f237c7fd4f..bdfe79f359 100644 --- a/trace-events +++ b/trace-events @@ -1383,6 +1383,10 @@ spapr_iommu_new_table(uint64_t liobn, void *tcet, void *table, int fd) "liobn=%" # hw/ppc/ppc.c ppc_tb_adjust(uint64_t offs1, uint64_t offs2, int64_t diff, int64_t seconds) "adjusted from 0x%"PRIx64" to 0x%"PRIx64", diff %"PRId64" (%"PRId64"s)" +# hw/ppc/prep.c +prep_io_800_writeb(uint32_t addr, uint32_t val) "0x%08" PRIx32 " => 0x%02" PRIx32 +prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRIx32 + # util/hbitmap.c hbitmap_iter_skip_words(const void *hb, void *hbi, uint64_t pos, unsigned long cur) "hb %p hbi %p pos %"PRId64" cur 0x%lx" hbitmap_reset(void *hb, uint64_t start, uint64_t count, uint64_t sbit, uint64_t ebit) "hb %p items %"PRIu64",%"PRIu64" bits %"PRIu64"..%"PRIu64