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target-arm: Implement ISR_EL1 register 

Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
This commit is contained in:
Peter Maydell 2014-04-15 19:18:46 +01:00
parent 2eef0bf821
commit 1090b9c6cc
1 changed files with 18 additions and 0 deletions
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18
target-arm/helper.c
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@ -665,6 +665,21 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
env->cp15.c0_cssel = value & 0xf; env->cp15.c0_cssel = value & 0xf;
} }
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
CPUState *cs = ENV_GET_CPU(env);
uint64_t ret = 0;
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
ret |= CPSR_I;
}
if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
ret |= CPSR_F;
}
/* External aborts are not possible in QEMU so A bit is always clear */
return ret;
}
static const ARMCPRegInfo v7_cp_reginfo[] = { static const ARMCPRegInfo v7_cp_reginfo[] = {
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
* debug components * debug components
@ -782,6 +797,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
.fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
.resetfn = arm_cp_reset_ignore }, .resetfn = arm_cp_reset_ignore },
{ .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
.type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };