Less hardcoding of TARGET_USER_ONLY.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/cpu.h

@@ -445,17 +445,12 @@ struct CPUMIPSState {
     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
     int insn_flags; /* Supported instruction set */
 
-#ifdef CONFIG_USER_ONLY
+    target_ulong tls_value; /* For usermode emulation */
-    target_ulong tls_value;
-#endif
 
     CPU_COMMON
 
     const mips_def_t *cpu_model;
-#ifndef CONFIG_USER_ONLY
     void *irq[8];
-#endif
-
     struct QEMUTimer *timer; /* Internal timer */
 };
 
@@ -494,7 +489,6 @@ static inline int cpu_mmu_index (CPUState *env)
     return env->hflags & MIPS_HFLAG_KSU;
 }
 
-#if defined(CONFIG_USER_ONLY)
 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 {
     if (newsp)
@@ -502,7 +496,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
     env->active_tc.gpr[7] = 0;
     env->active_tc.gpr[2] = 0;
 }
-#endif
 
 #include "cpu-all.h"
 

target-mips/helper.c

@@ -206,26 +206,23 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
     return ret;
 }
 
-#if defined(CONFIG_USER_ONLY)
 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 {
+    if (env->user_mode_only)
         return addr;
-}
+    else {
-#else
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
-{
         target_ulong phys_addr;
         int prot;
 
         if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
             return -1;
         return phys_addr;
+    }
 }
 
 void cpu_mips_init_mmu (CPUState *env)
 {
 }
-#endif /* !defined(CONFIG_USER_ONLY) */
 
 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                                int mmu_idx, int is_softmmu)
@@ -318,7 +315,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
     return ret;
 }
 
-#if !defined(CONFIG_USER_ONLY)
 static const char * const excp_names[EXCP_LAST + 1] = {
     [EXCP_RESET] = "reset",
     [EXCP_SRESET] = "soft reset",
@@ -354,11 +350,10 @@ static const char * const excp_names[EXCP_LAST + 1] = {
     [EXCP_C2E] = "precise coprocessor 2",
     [EXCP_CACHE] = "cache error",
 };
-#endif
 
 void do_interrupt (CPUState *env)
 {
-#if !defined(CONFIG_USER_ONLY)
+    if (!env->user_mode_only) {
         target_ulong offset;
         int cause = -1;
         const char *name;
@@ -380,10 +375,9 @@ void do_interrupt (CPUState *env)
         case EXCP_DSS:
             env->CP0_Debug |= 1 << CP0DB_DSS;
             /* Debug single step cannot be raised inside a delay slot and
-         * resume will always occur on the next instruction
+               resume will always occur on the next instruction
-         * (but we assume the pc has always been updated during
+               (but we assume the pc has always been updated during
-         *  code translation).
+               code translation). */
-         */
             env->CP0_DEPC = env->active_tc.PC;
             goto enter_debug_mode;
         case EXCP_DINT:
@@ -579,7 +573,7 @@ void do_interrupt (CPUState *env)
                     env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
                     env->CP0_DEPC);
         }
-#endif /* !defined(CONFIG_USER_ONLY) */
+    }
     env->exception_index = EXCP_NONE;
 }
 

target-mips/helper.h

@@ -41,8 +41,8 @@ DEF_HELPER(target_ulong, do_macchiu, (target_ulong t0, target_ulong t1))
 DEF_HELPER(target_ulong, do_msachi, (target_ulong t0, target_ulong t1))
 DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
 
-/* CP0 helpers */
 #ifndef CONFIG_USER_ONLY
+/* CP0 helpers */
 DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (void))
 DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (void))
 DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (void))
@@ -135,7 +135,6 @@ DEF_HELPER(void, do_mtc0_taglo, (target_ulong t0))
 DEF_HELPER(void, do_mtc0_datalo, (target_ulong t0))
 DEF_HELPER(void, do_mtc0_taghi, (target_ulong t0))
 DEF_HELPER(void, do_mtc0_datahi, (target_ulong t0))
-#endif /* !CONFIG_USER_ONLY */
 
 /* MIPS MT functions */
 DEF_HELPER(target_ulong, do_mftgpr, (target_ulong t0, uint32_t sel))
@@ -152,6 +151,7 @@ DEF_HELPER(target_ulong, do_dmt, (target_ulong t0))
 DEF_HELPER(target_ulong, do_emt, (target_ulong t0))
 DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0))
 DEF_HELPER(target_ulong, do_evpe, (target_ulong t0))
+#endif /* !CONFIG_USER_ONLY */
 DEF_HELPER(void, do_fork, (target_ulong t0, target_ulong t1))
 DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
 
@@ -257,10 +257,12 @@ FOP_PROTO(ngt)
 #undef FOP_PROTO
 
 /* Special functions */
+#ifndef CONFIG_USER_ONLY
 DEF_HELPER(target_ulong, do_di, (void))
 DEF_HELPER(target_ulong, do_ei, (void))
 DEF_HELPER(void, do_eret, (void))
 DEF_HELPER(void, do_deret, (void))
+#endif /* !CONFIG_USER_ONLY */
 DEF_HELPER(target_ulong, do_rdhwr_cpunum, (void))
 DEF_HELPER(target_ulong, do_rdhwr_synci_step, (void))
 DEF_HELPER(target_ulong, do_rdhwr_cc, (void))

target-mips/op_helper.c

@@ -596,59 +596,7 @@ void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
 }
 #endif /* TARGET_MIPS64 */
 
-#ifdef CONFIG_USER_ONLY
+#ifndef CONFIG_USER_ONLY
-void do_mfc0_random (void)
-{
-    cpu_abort(env, "mfc0 random\n");
-}
-
-void do_mfc0_count (void)
-{
-    cpu_abort(env, "mfc0 count\n");
-}
-
-void cpu_mips_store_count(CPUState *env, uint32_t value)
-{
-    cpu_abort(env, "mtc0 count\n");
-}
-
-void cpu_mips_store_compare(CPUState *env, uint32_t value)
-{
-    cpu_abort(env, "mtc0 compare\n");
-}
-
-void cpu_mips_start_count(CPUState *env)
-{
-    cpu_abort(env, "start count\n");
-}
-
-void cpu_mips_stop_count(CPUState *env)
-{
-    cpu_abort(env, "stop count\n");
-}
-
-void cpu_mips_update_irq(CPUState *env)
-{
-    cpu_abort(env, "mtc0 status / mtc0 cause\n");
-}
-
-void do_mtc0_status_debug(uint32_t old, uint32_t val)
-{
-    cpu_abort(env, "mtc0 status debug\n");
-}
-
-void do_mtc0_status_irqraise_debug (void)
-{
-    cpu_abort(env, "mtc0 status irqraise debug\n");
-}
-
-void cpu_mips_tlb_flush (CPUState *env, int flush_global)
-{
-    cpu_abort(env, "mips_tlb_flush\n");
-}
-
-#else
-
 /* CP0 helpers */
 target_ulong do_mfc0_mvpcontrol (void)
 {
@@ -1582,44 +1530,6 @@ target_ulong do_yield(target_ulong t0)
     return env->CP0_YQMask;
 }
 
-/* CP1 functions */
-void fpu_handle_exception(void)
-{
-#ifdef CONFIG_SOFTFLOAT
-    int flags = get_float_exception_flags(&env->fpu->fp_status);
-    unsigned int cpuflags = 0, enable, cause = 0;
-
-    enable = GET_FP_ENABLE(env->fpu->fcr31);
-
-    /* determine current flags */
-    if (flags & float_flag_invalid) {
-        cpuflags |= FP_INVALID;
-        cause |= FP_INVALID & enable;
-    }
-    if (flags & float_flag_divbyzero) {
-        cpuflags |= FP_DIV0;
-        cause |= FP_DIV0 & enable;
-    }
-    if (flags & float_flag_overflow) {
-        cpuflags |= FP_OVERFLOW;
-        cause |= FP_OVERFLOW & enable;
-    }
-    if (flags & float_flag_underflow) {
-        cpuflags |= FP_UNDERFLOW;
-        cause |= FP_UNDERFLOW & enable;
-    }
-    if (flags & float_flag_inexact) {
-        cpuflags |= FP_INEXACT;
-        cause |= FP_INEXACT & enable;
-    }
-    SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
-    SET_FP_CAUSE(env->fpu->fcr31, cause);
-#else
-    SET_FP_FLAGS(env->fpu->fcr31, 0);
-    SET_FP_CAUSE(env->fpu->fcr31, 0);
-#endif
-}
-
 #ifndef CONFIG_USER_ONLY
 /* TLB management */
 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
@@ -1743,8 +1653,6 @@ void r4k_do_tlbr (void)
                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 /* Specials */
 target_ulong do_di (void)
 {
@@ -1821,6 +1729,7 @@ void do_deret (void)
         debug_post_eret();
     env->CP0_LLAddr = 1;
 }
+#endif /* !CONFIG_USER_ONLY */
 
 target_ulong do_rdhwr_cpunum(void)
 {

target-mips/translate.c

@@ -2808,8 +2808,8 @@ fail:
     tcg_temp_free(t1);
 }
 
-/* CP0 (MMU and control) */
 #ifndef CONFIG_USER_ONLY
+/* CP0 (MMU and control) */
 static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
 {
     TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
@@ -8052,12 +8052,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
                     tcg_gen_helper_1_0(do_rdhwr_ccres, t0);
                     break;
                 case 29:
-#if defined (CONFIG_USER_ONLY)
+                    if (env->user_mode_only) {
                         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
                         break;
-#else
+                    } else {
-                    /* XXX: Some CPUs implement this in hardware. Not supported yet. */
+                        /* XXX: Some CPUs implement this in hardware.
-#endif
+                           Not supported yet. */
+                    }
                 default:            /* Invalid */
                     MIPS_INVAL("rdhwr");
                     generate_exception(ctx, EXCP_RI);
@@ -8166,20 +8167,22 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
         case OPC_DMTC0:
 #endif
 #ifndef CONFIG_USER_ONLY
+            if (!env->user_mode_only)
                 gen_cp0(env, ctx, op1, rt, rd);
-#endif
+#endif /* !CONFIG_USER_ONLY */
             break;
         case OPC_C0_FIRST ... OPC_C0_LAST:
 #ifndef CONFIG_USER_ONLY
+            if (!env->user_mode_only)
                 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
-#endif
+#endif /* !CONFIG_USER_ONLY */
             break;
         case OPC_MFMC0:
 #ifndef CONFIG_USER_ONLY
-            op2 = MASK_MFMC0(ctx->opcode);
+            if (!env->user_mode_only) {
-            {
                 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
 
+                op2 = MASK_MFMC0(ctx->opcode);
                 switch (op2) {
                 case OPC_DMT:
                     check_insn(env, ctx, ASE_MT);
@@ -8219,7 +8222,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
                 gen_store_gpr(t0, rt);
                 tcg_temp_free(t0);
             }
-#endif
+#endif /* !CONFIG_USER_ONLY */
             break;
         case OPC_RDPGPR:
             check_insn(env, ctx, ISA_MIPS32R2);
@@ -8474,11 +8477,10 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
     /* Restore delay slot state from the tb context.  */
     ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
     restore_cpu_state(env, &ctx);
-#if defined(CONFIG_USER_ONLY)
+    if (env->user_mode_only)
         ctx.mem_idx = MIPS_HFLAG_UM;
-#else
+    else
         ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
-#endif
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
     if (max_insns == 0)
@@ -8759,10 +8761,15 @@ void cpu_reset (CPUMIPSState *env)
     tlb_flush(env, 1);
 
     /* Minimal init */
-#if !defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_USER_ONLY)
+    env->user_mode_only = 1;
+#endif
+    if (env->user_mode_only) {
+        env->hflags = MIPS_HFLAG_UM;
+    } else {
         if (env->hflags & MIPS_HFLAG_BMASK) {
             /* If the exception was raised from a delay slot,
-         * come back to the jump.  */
+               come back to the jump.  */
             env->CP0_ErrorEPC = env->active_tc.PC - 4;
         } else {
             env->CP0_ErrorEPC = env->active_tc.PC;
@@ -8787,14 +8794,9 @@ void cpu_reset (CPUMIPSState *env)
         }
         /* Count register increments in debug mode, EJTAG version 1 */
         env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
-#endif
-    env->exception_index = EXCP_NONE;
-#if defined(CONFIG_USER_ONLY)
-    env->hflags = MIPS_HFLAG_UM;
-    env->user_mode_only = 1;
-#else
         env->hflags = MIPS_HFLAG_CP0;
-#endif
+    }
+    env->exception_index = EXCP_NONE;
     cpu_mips_register(env, env->cpu_model);
 }
 

target-mips/translate_init.c

@@ -439,7 +439,6 @@ void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
     }
 }
 
-#ifndef CONFIG_USER_ONLY
 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1;
@@ -485,21 +484,20 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
     env->CP0_Random = env->tlb->nb_tlb - 1;
     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
-#endif /* CONFIG_USER_ONLY */
 
 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 {
     env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
 
     env->fpu->fcr0 = def->CP1_fcr0;
-#ifdef CONFIG_USER_ONLY
+    if (env->user_mode_only) {
         if (env->CP0_Config1 & (1 << CP0C1_FP))
             env->hflags |= MIPS_HFLAG_FPU;
 #ifdef TARGET_MIPS64
         if (env->fpu->fcr0 & (1 << FCR0_F64))
             env->hflags |= MIPS_HFLAG_F64;
 #endif
-#endif
+    }
 }
 
 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
@@ -512,15 +510,15 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
        implemented, 5 TCs implemented. */
     env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
-#ifndef CONFIG_USER_ONLY
-                             /* Usermode has no TLB support */
-                             (env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
-#endif
 // TODO: actually do 2 VPEs.
 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
 //                             (0x04 << CP0MVPC0_PTC);
                              (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
                              (0x04 << CP0MVPC0_PTC);
+    /* Usermode has no TLB support */
+    if (!env->user_mode_only)
+        env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+
     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
     env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
@@ -568,9 +566,8 @@ static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
     env->CP0_SRSConf4 = def->CP0_SRSConf4;
     env->insn_flags = def->insn_flags;
 
-#ifndef CONFIG_USER_ONLY
+    if (!env->user_mode_only)
         mmu_init(env, def);
-#endif
     fpu_init(env, def);
     mvp_init(env, def);
     return 0;