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xilinx_axienet: convert to memory API 

Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-11-15 12:26:54 +02:00
parent f810bc4ab6
commit 0dc31f3b32
1 changed files with 11 additions and 18 deletions
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29
hw/xilinx_axienet.c
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@ -308,6 +308,7 @@ struct TEMAC {
struct XilinxAXIEnet { struct XilinxAXIEnet {
SysBusDevice busdev; SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq; qemu_irq irq;
void *dmach; void *dmach;
NICState *nic; NICState *nic;
@ -411,7 +412,7 @@ static void enet_update_irq(struct XilinxAXIEnet *s)
qemu_set_irq(s->irq, !!s->regs[R_IP]); qemu_set_irq(s->irq, !!s->regs[R_IP]);
} }
static uint32_t enet_readl(void *opaque, target_phys_addr_t addr) static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
{ {
struct XilinxAXIEnet *s = opaque; struct XilinxAXIEnet *s = opaque;
uint32_t r = 0; uint32_t r = 0;
@ -502,8 +503,8 @@ static uint32_t enet_readl(void *opaque, target_phys_addr_t addr)
return r; return r;
} }
static void static void enet_write(void *opaque, target_phys_addr_t addr,
enet_writel(void *opaque, target_phys_addr_t addr, uint32_t value) uint64_t value, unsigned size)
{ {
struct XilinxAXIEnet *s = opaque; struct XilinxAXIEnet *s = opaque;
struct TEMAC *t = &s->TEMAC; struct TEMAC *t = &s->TEMAC;
@ -596,7 +597,7 @@ enet_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
default: default:
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
__func__, addr * 4, value)); __func__, addr * 4, (unsigned)value));
if (addr < ARRAY_SIZE(s->regs)) { if (addr < ARRAY_SIZE(s->regs)) {
s->regs[addr] = value; s->regs[addr] = value;
} }
@ -605,16 +606,10 @@ enet_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
enet_update_irq(s); enet_update_irq(s);
} }
static CPUReadMemoryFunc * const enet_read[] = { static const MemoryRegionOps enet_ops = {
&enet_readl, .read = enet_read,
&enet_readl, .write = enet_write,
&enet_readl, .endianness = DEVICE_LITTLE_ENDIAN,
};
static CPUWriteMemoryFunc * const enet_write[] = {
&enet_writel,
&enet_writel,
&enet_writel,
}; };
static int eth_can_rx(VLANClientState *nc) static int eth_can_rx(VLANClientState *nc)
@ -847,7 +842,6 @@ static NetClientInfo net_xilinx_enet_info = {
static int xilinx_enet_init(SysBusDevice *dev) static int xilinx_enet_init(SysBusDevice *dev)
{ {
struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev); struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
int enet_regs;
sysbus_init_irq(dev, &s->irq); sysbus_init_irq(dev, &s->irq);
@ -857,9 +851,8 @@ static int xilinx_enet_init(SysBusDevice *dev)
xlx_dma_connect_client(s->dmach, s, axienet_stream_push); xlx_dma_connect_client(s->dmach, s, axienet_stream_push);
enet_regs = cpu_register_io_memory(enet_read, enet_write, s, memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000);
DEVICE_LITTLE_ENDIAN); sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, 0x40000, enet_regs);
qemu_macaddr_default_if_unset(&s->conf.macaddr); qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,