mirror of https://github.com/xqemu/xqemu.git
hw/intc/arm_gic: Implement Non-secure view of RPR
For GICs with Security Extensions Non-secure reads have a restricted view on the current running priority. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-10-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-11-git-send-email-greg.bellows@linaro.org [PMM: make function static, minor comment tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -286,6 +286,23 @@ static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value,
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(s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis");
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(s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis");
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}
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}
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static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs)
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{
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if (s->security_extn && !attrs.secure) {
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if (s->running_priority[cpu] & 0x80) {
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/* Running priority in upper half of range: return the Non-secure
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* view of the priority.
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*/
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return s->running_priority[cpu] << 1;
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} else {
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/* Running priority in lower half of range: RAZ */
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return 0;
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}
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} else {
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return s->running_priority[cpu];
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}
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}
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void gic_complete_irq(GICState *s, int cpu, int irq)
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void gic_complete_irq(GICState *s, int cpu, int irq)
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{
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{
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int update = 0;
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int update = 0;
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@ -817,7 +834,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
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*data = gic_acknowledge_irq(s, cpu);
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*data = gic_acknowledge_irq(s, cpu);
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break;
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break;
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case 0x14: /* Running Priority */
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case 0x14: /* Running Priority */
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*data = s->running_priority[cpu];
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*data = gic_get_running_priority(s, cpu, attrs);
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break;
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break;
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case 0x18: /* Highest Pending Interrupt */
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case 0x18: /* Highest Pending Interrupt */
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*data = s->current_pending[cpu];
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*data = s->current_pending[cpu];
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