mirror of https://github.com/xqemu/xqemu.git
vmstate: port pl022 ssp
Signed-off-by: Juan Quintela <quintela@redhat.com>
This commit is contained in:
parent
293c16aa37
commit
075790c2c2
84
hw/pl022.c
84
hw/pl022.c
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@ -239,54 +239,42 @@ static CPUWriteMemoryFunc * const pl022_writefn[] = {
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pl022_write
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pl022_write
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};
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};
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static void pl022_save(QEMUFile *f, void *opaque)
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static const VMStateDescription vmstate_pl022 = {
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{
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.name = "pl022_ssp",
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pl022_state *s = (pl022_state *)opaque;
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.version_id = 1,
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int i;
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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qemu_put_be32(f, s->cr0);
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.fields = (VMStateField[]) {
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qemu_put_be32(f, s->cr1);
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VMSTATE_UINT32(cr0, pl022_state),
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qemu_put_be32(f, s->bitmask);
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VMSTATE_UINT32(cr1, pl022_state),
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qemu_put_be32(f, s->sr);
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VMSTATE_UINT32(bitmask, pl022_state),
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qemu_put_be32(f, s->cpsr);
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VMSTATE_UINT32(sr, pl022_state),
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qemu_put_be32(f, s->is);
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VMSTATE_UINT32(cpsr, pl022_state),
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qemu_put_be32(f, s->im);
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VMSTATE_UINT32(is, pl022_state),
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qemu_put_be32(f, s->tx_fifo_head);
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VMSTATE_UINT32(im, pl022_state),
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qemu_put_be32(f, s->rx_fifo_head);
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VMSTATE_INT32(tx_fifo_head, pl022_state),
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qemu_put_be32(f, s->tx_fifo_len);
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VMSTATE_INT32(rx_fifo_head, pl022_state),
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qemu_put_be32(f, s->rx_fifo_len);
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VMSTATE_INT32(tx_fifo_len, pl022_state),
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for (i = 0; i < 8; i++) {
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VMSTATE_INT32(rx_fifo_len, pl022_state),
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qemu_put_be16(f, s->tx_fifo[i]);
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VMSTATE_UINT16(tx_fifo[0], pl022_state),
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qemu_put_be16(f, s->rx_fifo[i]);
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VMSTATE_UINT16(rx_fifo[0], pl022_state),
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VMSTATE_UINT16(tx_fifo[1], pl022_state),
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VMSTATE_UINT16(rx_fifo[1], pl022_state),
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VMSTATE_UINT16(tx_fifo[2], pl022_state),
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VMSTATE_UINT16(rx_fifo[2], pl022_state),
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VMSTATE_UINT16(tx_fifo[3], pl022_state),
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VMSTATE_UINT16(rx_fifo[3], pl022_state),
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VMSTATE_UINT16(tx_fifo[4], pl022_state),
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VMSTATE_UINT16(rx_fifo[4], pl022_state),
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VMSTATE_UINT16(tx_fifo[5], pl022_state),
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VMSTATE_UINT16(rx_fifo[5], pl022_state),
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VMSTATE_UINT16(tx_fifo[6], pl022_state),
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VMSTATE_UINT16(rx_fifo[6], pl022_state),
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VMSTATE_UINT16(tx_fifo[7], pl022_state),
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VMSTATE_UINT16(rx_fifo[7], pl022_state),
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VMSTATE_END_OF_LIST()
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}
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}
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}
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};
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static int pl022_load(QEMUFile *f, void *opaque, int version_id)
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{
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pl022_state *s = (pl022_state *)opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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s->cr0 = qemu_get_be32(f);
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s->cr1 = qemu_get_be32(f);
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s->bitmask = qemu_get_be32(f);
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s->sr = qemu_get_be32(f);
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s->cpsr = qemu_get_be32(f);
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s->is = qemu_get_be32(f);
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s->im = qemu_get_be32(f);
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s->tx_fifo_head = qemu_get_be32(f);
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s->rx_fifo_head = qemu_get_be32(f);
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s->tx_fifo_len = qemu_get_be32(f);
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s->rx_fifo_len = qemu_get_be32(f);
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for (i = 0; i < 8; i++) {
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s->tx_fifo[i] = qemu_get_be16(f);
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s->rx_fifo[i] = qemu_get_be16(f);
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}
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return 0;
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}
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static int pl022_init(SysBusDevice *dev)
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static int pl022_init(SysBusDevice *dev)
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{
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{
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@ -300,7 +288,7 @@ static int pl022_init(SysBusDevice *dev)
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(dev, &s->irq);
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s->ssi = ssi_create_bus(&dev->qdev, "ssi");
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s->ssi = ssi_create_bus(&dev->qdev, "ssi");
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pl022_reset(s);
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pl022_reset(s);
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register_savevm(&dev->qdev, "pl022_ssp", -1, 1, pl022_save, pl022_load, s);
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vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);
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return 0;
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return 0;
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}
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}
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