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target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} 

The exception is not emitted anymore; remove it and the associated
TCG variables.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1467054136-10430-31-git-send-email-cota@braap.org>
This commit is contained in:
Emilio G. Cota 2016-06-27 15:02:16 -04:00 committed by Richard Henderson
parent f4e6eb7ffe
commit 05188cc72f
4 changed files with 1 additions and 22 deletions
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5
target-arm/cpu.h
View File

@ -46,7 +46,6 @@
#define EXCP_BKPT 7 #define EXCP_BKPT 7
#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
#define EXCP_STREX 10
#define EXCP_HVC 11 /* HyperVisor Call */ #define EXCP_HVC 11 /* HyperVisor Call */
#define EXCP_HYP_TRAP 12 #define EXCP_HYP_TRAP 12
#define EXCP_SMC 13 /* Secure Monitor Call */ #define EXCP_SMC 13 /* Secure Monitor Call */
@ -475,10 +474,6 @@ typedef struct CPUARMState {
uint64_t exclusive_addr; uint64_t exclusive_addr;
uint64_t exclusive_val; uint64_t exclusive_val;
uint64_t exclusive_high; uint64_t exclusive_high;
#if defined(CONFIG_USER_ONLY)
uint64_t exclusive_test;
uint32_t exclusive_info;
#endif
/* iwMMXt coprocessor state. */ /* iwMMXt coprocessor state. */
struct { struct {

4
target-arm/internals.h
View File

@ -46,8 +46,7 @@ static inline bool excp_is_internal(int excp)
|| excp == EXCP_HALTED || excp == EXCP_HALTED
|| excp == EXCP_EXCEPTION_EXIT || excp == EXCP_EXCEPTION_EXIT
|| excp == EXCP_KERNEL_TRAP || excp == EXCP_KERNEL_TRAP
|| excp == EXCP_SEMIHOST || excp == EXCP_SEMIHOST;
|| excp == EXCP_STREX;
} }
/* Exception names for debug logging; note that not all of these /* Exception names for debug logging; note that not all of these
@ -63,7 +62,6 @@ static const char * const excnames[] = {
[EXCP_BKPT] = "Breakpoint", [EXCP_BKPT] = "Breakpoint",
[EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
[EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
[EXCP_STREX] = "QEMU intercept of STREX",
[EXCP_HVC] = "Hypervisor Call", [EXCP_HVC] = "Hypervisor Call",
[EXCP_HYP_TRAP] = "Hypervisor Trap", [EXCP_HYP_TRAP] = "Hypervisor Trap",
[EXCP_SMC] = "Secure Monitor Call", [EXCP_SMC] = "Secure Monitor Call",

10
target-arm/translate.c
View File

@ -65,10 +65,6 @@ static TCGv_i32 cpu_R[16];
TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_addr;
TCGv_i64 cpu_exclusive_val; TCGv_i64 cpu_exclusive_val;
#ifdef CONFIG_USER_ONLY
TCGv_i64 cpu_exclusive_test;
TCGv_i32 cpu_exclusive_info;
#endif
/* FIXME: These should be removed. */ /* FIXME: These should be removed. */
static TCGv_i32 cpu_F0s, cpu_F1s; static TCGv_i32 cpu_F0s, cpu_F1s;
@ -102,12 +98,6 @@ void arm_translate_init(void)
offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env, cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUARMState, exclusive_val), "exclusive_val"); offsetof(CPUARMState, exclusive_val), "exclusive_val");
#ifdef CONFIG_USER_ONLY
cpu_exclusive_test = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUARMState, exclusive_test), "exclusive_test");
cpu_exclusive_info = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUARMState, exclusive_info), "exclusive_info");
#endif
a64_translate_init(); a64_translate_init();
} }

4
target-arm/translate.h
View File

@ -79,10 +79,6 @@ extern TCGv_env cpu_env;
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_addr;
extern TCGv_i64 cpu_exclusive_val; extern TCGv_i64 cpu_exclusive_val;
#ifdef CONFIG_USER_ONLY
extern TCGv_i64 cpu_exclusive_test;
extern TCGv_i32 cpu_exclusive_info;
#endif
static inline int arm_dc_feature(DisasContext *dc, int feature) static inline int arm_dc_feature(DisasContext *dc, int feature)
{ {