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Merge remote-tracking branch 'qemu-kvm/memory/batch' into staging

This commit is contained in:
Anthony Liguori 2011-12-05 08:43:38 -06:00
parent 4eb2d2d900 f44336c594
commit 01e7a53aed
168 changed files with 2391 additions and 2725 deletions
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2
hw/an5206.c
View File

@ -53,7 +53,7 @@ static void an5206_init(ram_addr_t ram_size,
memory_region_init_ram(sram, NULL, "an5206.sram", 512);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(AN5206_MBAR_ADDR, env);
mcf5206_init(address_space_mem, AN5206_MBAR_ADDR, env);
/* Load kernel. */
if (!kernel_filename) {

6
hw/apb_pci.c
View File

@ -410,18 +410,18 @@ static int pci_pbm_init_device(SysBusDevice *dev)
memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
0x10000);
/* at region 0 */
sysbus_init_mmio_region(dev, &s->apb_config);
sysbus_init_mmio(dev, &s->apb_config);
memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
0x1000000);
/* at region 1 */
sysbus_init_mmio_region(dev, &s->pci_config);
sysbus_init_mmio(dev, &s->pci_config);
/* pci_ioport */
memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
"apb-pci-ioport", 0x10000);
/* at region 2 */
sysbus_init_mmio_region(dev, &s->pci_ioport);
sysbus_init_mmio(dev, &s->pci_ioport);
return 0;
}

2
hw/apic.c
View File

@ -998,7 +998,7 @@ static int apic_init1(SysBusDevice *dev)
}
memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
MSI_ADDR_SIZE);
sysbus_init_mmio_region(dev, &s->io_memory);
sysbus_init_mmio(dev, &s->io_memory);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
s->idx = last_apic_idx++;

2
hw/arm11mpcore.c
View File

@ -73,7 +73,7 @@ static int realview_mpcore_init(SysBusDevice *dev)
}
}
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
sysbus_init_mmio_region(dev, sysbus_mmio_get_region(s->priv, 0));
sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
return 0;
}

2
hw/arm_sysctl.c
View File

@ -383,7 +383,7 @@ static int arm_sysctl_init1(SysBusDevice *dev)
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
return 0;

4
hw/arm_timer.c
View File

@ -247,7 +247,7 @@ static int sp804_init(SysBusDevice *dev)
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
@ -311,7 +311,7 @@ static int icp_pit_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[2]->irq);
memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
/* This device has no state to save/restore. The component timers will
save themselves. */
return 0;

2
hw/armv7m.c
View File

@ -126,7 +126,7 @@ static int bitband_init(SysBusDevice *dev)
memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
0x02000000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}

63
hw/axis_dev88.c
View File

@ -39,6 +39,7 @@
struct nand_state_t
{
DeviceState *nand;
MemoryRegion iomem;
unsigned int rdy:1;
unsigned int ale:1;
unsigned int cle:1;
@ -46,7 +47,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t r;
@ -61,31 +62,25 @@ static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
}
static void
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
struct nand_state_t *s = opaque;
int rdy;
DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
nand_setio(s->nand, value);
nand_getpins(s->nand, &rdy);
s->rdy = rdy;
}
static CPUReadMemoryFunc * const nand_read[] = {
&nand_readl,
&nand_readl,
&nand_readl,
static const MemoryRegionOps nand_ops = {
.read = nand_read,
.write = nand_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const nand_write[] = {
&nand_writel,
&nand_writel,
&nand_writel,
};
struct tempsensor_t
{
unsigned int shiftreg;
@ -165,12 +160,13 @@ static void tempsensor_clkedge(struct tempsensor_t *s,
static struct gpio_state_t
{
MemoryRegion iomem;
struct nand_state_t *nand;
struct tempsensor_t tempsensor;
uint32_t regs[0x5c / 4];
} gpio_state;
static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@ -199,10 +195,11 @@ static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
D(printf("%s %x=%x\n", __func__, addr, r));
}
static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
struct gpio_state_t *s = opaque;
D(printf("%s %x=%x\n", __func__, addr, value));
D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
addr >>= 2;
switch (addr)
@ -230,14 +227,14 @@ static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static CPUReadMemoryFunc * const gpio_read[] = {
NULL, NULL,
&gpio_readl,
};
static CPUWriteMemoryFunc * const gpio_write[] = {
NULL, NULL,
&gpio_writel,
static const MemoryRegionOps gpio_ops = {
.read = gpio_read,
.write = gpio_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
#define INTMEM_SIZE (128 * 1024)
@ -258,8 +255,6 @@ void axisdev88_init (ram_addr_t ram_size,
void *etraxfs_dmac;
struct etraxfs_dma_client *dma_eth;
int i;
int nand_regs;
int gpio_regs;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
@ -283,14 +278,16 @@ void axisdev88_init (ram_addr_t ram_size,
nand = drive_get(IF_MTD, 0, 0);
nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
NAND_MFR_STMICRO, 0x39);
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
memory_region_init_io(&nand_state.iomem, &nand_ops, &nand_state,
"nand", 0x05000000);
memory_region_add_subregion(address_space_mem, 0x10000000,
&nand_state.iomem);
gpio_state.nand = &nand_state;
gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
memory_region_init_io(&gpio_state.iomem, &gpio_ops, &gpio_state,
"gpio", 0x5c);
memory_region_add_subregion(address_space_mem, 0x3001a000,
&gpio_state.iomem);
cpu_irq = cris_pic_init_cpu(env);

4
hw/bitbang_i2c.c
View File

@ -184,6 +184,7 @@ bitbang_i2c_interface *bitbang_i2c_init(i2c_bus *bus)
/* GPIO interface. */
typedef struct {
SysBusDevice busdev;
MemoryRegion dummy_iomem;
bitbang_i2c_interface *bitbang;
int last_level;
qemu_irq out;
@ -205,7 +206,8 @@ static int gpio_i2c_init(SysBusDevice *dev)
GPIOI2CState *s = FROM_SYSBUS(GPIOI2CState, dev);
i2c_bus *bus;
sysbus_init_mmio(dev, 0x0, 0);
memory_region_init(&s->dummy_iomem, "gpio_i2c", 0);
sysbus_init_mmio(dev, &s->dummy_iomem);
bus = i2c_init_bus(&dev->qdev, "i2c");
s->bitbang = bitbang_i2c_init(bus);

199
hw/bonito.c
View File

@ -201,17 +201,9 @@ typedef struct PCIBonitoState
} boncop;
/* Bonito registers */
target_phys_addr_t bonito_reg_start;
target_phys_addr_t bonito_reg_length;
int bonito_reg_handle;
target_phys_addr_t bonito_pciconf_start;
target_phys_addr_t bonito_pciconf_length;
int bonito_pciconf_handle;
target_phys_addr_t bonito_spciconf_start;
target_phys_addr_t bonito_spciconf_length;
int bonito_spciconf_handle;
MemoryRegion iomem;
MemoryRegion iomem_ldma;
MemoryRegion iomem_cop;
target_phys_addr_t bonito_pciio_start;
target_phys_addr_t bonito_pciio_length;
@ -221,19 +213,12 @@ typedef struct PCIBonitoState
target_phys_addr_t bonito_localio_length;
int bonito_localio_handle;
target_phys_addr_t bonito_ldma_start;
target_phys_addr_t bonito_ldma_length;
int bonito_ldma_handle;
target_phys_addr_t bonito_cop_start;
target_phys_addr_t bonito_cop_length;
int bonito_cop_handle;
} PCIBonitoState;
PCIBonitoState * bonito_state;
static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void bonito_writel(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
@ -295,7 +280,8 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
@ -311,20 +297,18 @@ static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
}
}
static CPUWriteMemoryFunc * const bonito_write[] = {
NULL,
NULL,
bonito_writel,
};
static CPUReadMemoryFunc * const bonito_read[] = {
NULL,
NULL,
bonito_readl,
static const MemoryRegionOps bonito_ops = {
.read = bonito_readl,
.write = bonito_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@ -332,7 +316,8 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
s->dev.config_write(&s->dev, addr, val, 4);
}
static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PCIBonitoState *s = opaque;
@ -342,19 +327,19 @@ static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
}
/* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
static CPUWriteMemoryFunc * const bonito_pciconf_write[] = {
NULL,
NULL,
bonito_pciconf_writel,
static const MemoryRegionOps bonito_pciconf_ops = {
.read = bonito_pciconf_readl,
.write = bonito_pciconf_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static CPUReadMemoryFunc * const bonito_pciconf_read[] = {
NULL,
NULL,
bonito_pciconf_readl,
};
static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
@ -365,26 +350,25 @@ static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
}
static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
static CPUWriteMemoryFunc * const bonito_ldma_write[] = {
NULL,
NULL,
bonito_ldma_writel,
static const MemoryRegionOps bonito_ldma_ops = {
.read = bonito_ldma_readl,
.write = bonito_ldma_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static CPUReadMemoryFunc * const bonito_ldma_read[] = {
NULL,
NULL,
bonito_ldma_readl,
};
static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
@ -395,23 +379,21 @@ static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
}
static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
static CPUWriteMemoryFunc * const bonito_cop_write[] = {
NULL,
NULL,
bonito_cop_writel,
};
static CPUReadMemoryFunc * const bonito_cop_read[] = {
NULL,
NULL,
bonito_cop_readl,
static const MemoryRegionOps bonito_cop_ops = {
.read = bonito_cop_readl,
.write = bonito_cop_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
@ -602,16 +584,20 @@ static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
}
/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
static CPUWriteMemoryFunc * const bonito_spciconf_write[] = {
bonito_spciconf_writeb,
bonito_spciconf_writew,
bonito_spciconf_writel,
};
static CPUReadMemoryFunc * const bonito_spciconf_read[] = {
bonito_spciconf_readb,
bonito_spciconf_readw,
bonito_spciconf_readl,
static const MemoryRegionOps bonito_spciconf_ops = {
.old_mmio = {
.read = {
bonito_spciconf_readb,
bonito_spciconf_readw,
bonito_spciconf_readl,
},
.write = {
bonito_spciconf_writeb,
bonito_spciconf_writew,
bonito_spciconf_writel,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define BONITO_IRQ_BASE 32
@ -690,51 +676,38 @@ static int bonito_pcihost_initfn(SysBusDevice *dev)
static int bonito_initfn(PCIDevice *dev)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
SysBusDevice *sysbus = &s->pcihost->busdev;
/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
pci_config_set_prog_interface(dev->config, 0x00);
/* set the north bridge register mapping */
s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
s->bonito_reg_handle);
memory_region_init_io(&s->iomem, &bonito_ops, s,
"north-bridge-register", BONITO_INTERNAL_REG_SIZE);
sysbus_init_mmio(sysbus, &s->iomem);
sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
/* set the north bridge pci configure mapping */
s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
bonito_pciconf_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
s->bonito_pciconf_handle);
memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s,
"north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
sysbus_init_mmio(sysbus, &s->pcihost->conf_mem);
sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
/* set the south bridge pci configure mapping */
s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
bonito_spciconf_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
s->bonito_spciconf_handle);
memory_region_init_io(&s->pcihost->data_mem, &bonito_spciconf_ops, s,
"south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
sysbus_init_mmio(sysbus, &s->pcihost->data_mem);
sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
bonito_ldma_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_ldma_start = 0xbfe00200;
s->bonito_ldma_length = 0x100;
cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
s->bonito_ldma_handle);
memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s,
"ldma", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_ldma);
sysbus_mmio_map(sysbus, 3, 0xbfe00200);
s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
bonito_cop_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_cop_start = 0xbfe00300;
s->bonito_cop_length = 0x100;
cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,
s->bonito_cop_handle);
memory_region_init_io(&s->iomem_cop, &bonito_cop_ops, s,
"cop", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_cop);
sysbus_mmio_map(sysbus, 4, 0xbfe00300);
/* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
s->bonito_pciio_start = BONITO_PCIIO_BASE;
@ -780,10 +753,12 @@ PCIBus *bonito_init(qemu_irq *pic)
pcihost->bus = b;
qdev_init_nofail(dev);
d = pci_create_simple(b, PCI_DEVFN(0, 0), "Bonito");
/* set the pcihost pointer before bonito_initfn is called */
d = pci_create(b, PCI_DEVFN(0, 0), "Bonito");
s = DO_UPCAST(PCIBonitoState, dev, d);
s->pcihost = pcihost;
bonito_state = s;
qdev_init_nofail(&d->qdev);
return b;
}

27
hw/cs4231.c
View File

@ -35,6 +35,7 @@
typedef struct CSState {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
uint32_t regs[CS_REGS];
uint8_t dregs[CS_DREGS];
@ -54,7 +55,8 @@ static void cs_reset(DeviceState *d)
s->dregs[25] = CS_VER;
}
static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
CSState *s = opaque;
uint32_t saddr, ret;
@ -80,7 +82,8 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
return ret;
}
static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void cs_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
CSState *s = opaque;
uint32_t saddr;
@ -119,16 +122,10 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static CPUReadMemoryFunc * const cs_mem_read[3] = {
cs_mem_readl,
cs_mem_readl,
cs_mem_readl,
};
static CPUWriteMemoryFunc * const cs_mem_write[3] = {
cs_mem_writel,
cs_mem_writel,
cs_mem_writel,
static const MemoryRegionOps cs_mem_ops = {
.read = cs_mem_read,
.write = cs_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_cs4231 = {
@ -145,12 +142,10 @@ static const VMStateDescription vmstate_cs4231 = {
static int cs4231_init1(SysBusDevice *dev)
{
int io;
CSState *s = FROM_SYSBUS(CSState, dev);
io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, CS_SIZE, io);
memory_region_init_io(&s->iomem, &cs_mem_ops, s, "cs4321", CS_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
return 0;

4
hw/dec_pci.c
View File

@ -87,8 +87,8 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-data-idx", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
sysbus_init_mmio(dev, &s->host_state.conf_mem);
sysbus_init_mmio(dev, &s->host_state.data_mem);
return 0;
}

30
hw/dp8393x.c
View File

@ -156,7 +156,8 @@ typedef struct dp8393xState {
int64_t wt_last_update;
NICConf conf;
NICState *nic;
int mmio_index;
MemoryRegion *address_space;
MemoryRegion mmio;
/* Registers */
uint8_t cam[16][6];
@ -664,16 +665,12 @@ static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
}
static CPUReadMemoryFunc * const dp8393x_read[3] = {
dp8393x_readb,
dp8393x_readw,
dp8393x_readl,
};
static CPUWriteMemoryFunc * const dp8393x_write[3] = {
dp8393x_writeb,
dp8393x_writew,
dp8393x_writel,
static const MemoryRegionOps dp8393x_ops = {
.old_mmio = {
.read = { dp8393x_readb, dp8393x_readw, dp8393x_readl, },
.write = { dp8393x_writeb, dp8393x_writew, dp8393x_writel, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int nic_can_receive(VLANClientState *nc)
@ -865,7 +862,8 @@ static void nic_cleanup(VLANClientState *nc)
{
dp8393xState *s = DO_UPCAST(NICState, nc, nc)->opaque;
cpu_unregister_io_memory(s->mmio_index);
memory_region_del_subregion(s->address_space, &s->mmio);
memory_region_destroy(&s->mmio);
qemu_del_timer(s->watchdog);
qemu_free_timer(s->watchdog);
@ -882,6 +880,7 @@ static NetClientInfo net_dp83932_info = {
};
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
{
@ -891,6 +890,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
s = g_malloc0(sizeof(dp8393xState));
s->address_space = address_space;
s->mem_opaque = mem_opaque;
s->memory_rw = memory_rw;
s->it_shift = it_shift;
@ -908,7 +908,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_register_reset(nic_reset, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
memory_region_init_io(&s->mmio, &dp8393x_ops, s,
"dp8393x", 0x40 << it_shift);
memory_region_add_subregion(address_space, base, &s->mmio);
}

62
hw/ds1225y.c
View File

@ -27,13 +27,14 @@
typedef struct {
DeviceState qdev;
MemoryRegion iomem;
uint32_t chip_size;
char *filename;
FILE *file;
uint8_t *contents;
} NvRamState;
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
NvRamState *s = opaque;
uint32_t val;
@ -43,25 +44,8 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
v |= nvram_readb(opaque, addr + 1) << 8;
return v;
}
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
v |= nvram_readb(opaque, addr + 1) << 8;
v |= nvram_readb(opaque, addr + 2) << 16;
v |= nvram_readb(opaque, addr + 3) << 24;
return v;
}
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_write(void *opaque, target_phys_addr_t addr, uint64_t val,
unsigned size)
{
NvRamState *s = opaque;
@ -76,30 +60,14 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
nvram_writeb(opaque, addr + 2, (val >> 16) & 0xff);
nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
static CPUReadMemoryFunc * const nvram_read[] = {
&nvram_readb,
&nvram_readw,
&nvram_readl,
};
static CPUWriteMemoryFunc * const nvram_write[] = {
&nvram_writeb,
&nvram_writew,
&nvram_writel,
static const MemoryRegionOps nvram_ops = {
.read = nvram_read,
.write = nvram_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int nvram_post_load(void *opaque, int version_id)
@ -146,13 +114,11 @@ static int nvram_sysbus_initfn(SysBusDevice *dev)
{
NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
FILE *file;
int s_io;
s->contents = g_malloc0(s->chip_size);
s_io = cpu_register_io_memory(nvram_read, nvram_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->chip_size, s_io);
memory_region_init_io(&s->iomem, &nvram_ops, s, "nvram", s->chip_size);
sysbus_init_mmio(dev, &s->iomem);
/* Read current file */
file = fopen(s->filename, "rb");

63
hw/eccmemctl.c
View File

@ -122,13 +122,15 @@
typedef struct ECCState {
SysBusDevice busdev;
MemoryRegion iomem, iomem_diag;
qemu_irq irq;
uint32_t regs[ECC_NREGS];
uint8_t diag[ECC_DIAG_SIZE];
uint32_t version;
} ECCState;
static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
unsigned size)
{
ECCState *s = opaque;
@ -170,7 +172,8 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
ECCState *s = opaque;
uint32_t ret = 0;
@ -216,20 +219,18 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
return ret;
}
static CPUReadMemoryFunc * const ecc_mem_read[3] = {
NULL,
NULL,
ecc_mem_readl,
static const MemoryRegionOps ecc_mem_ops = {
.read = ecc_mem_read,
.write = ecc_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
NULL,
NULL,
ecc_mem_writel,
};
static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
ECCState *s = opaque;
@ -237,7 +238,8 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
static uint64_t ecc_diag_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
ECCState *s = opaque;
uint32_t ret = s->diag[(int)addr];
@ -246,16 +248,14 @@ static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
return ret;
}
static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = {
ecc_diag_mem_readb,
NULL,
NULL,
};
static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = {
ecc_diag_mem_writeb,
NULL,
NULL,
static const MemoryRegionOps ecc_diag_mem_ops = {
.read = ecc_diag_mem_read,
.write = ecc_diag_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static const VMStateDescription vmstate_ecc = {
@ -292,20 +292,17 @@ static void ecc_reset(DeviceState *d)
static int ecc_init1(SysBusDevice *dev)
{
int ecc_io_memory;
ECCState *s = FROM_SYSBUS(ECCState, dev);
sysbus_init_irq(dev, &s->irq);
s->regs[0] = s->version;
ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
memory_region_init_io(&s->iomem, &ecc_mem_ops, s, "ecc", ECC_SIZE);
sysbus_init_mmio(dev, &s->iomem);
if (s->version == ECC_MCC) { // SS-600MP only
ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
ecc_diag_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
memory_region_init_io(&s->iomem_diag, &ecc_diag_mem_ops, s,
"ecc.diag", ECC_DIAG_SIZE);
sysbus_init_mmio(dev, &s->iomem_diag);
}
return 0;

32
hw/empty_slot.c
View File

@ -24,31 +24,27 @@
typedef struct EmptySlot {
SysBusDevice busdev;
MemoryRegion iomem;
uint64_t size;
} EmptySlot;
static uint32_t empty_slot_readl(void *opaque, target_phys_addr_t addr)
static uint64_t empty_slot_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
DPRINTF("read from " TARGET_FMT_plx "\n", addr);
return 0;
}
static void empty_slot_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
static void empty_slot_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", val, addr);
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
}
CPUReadMemoryFunc * const empty_slot_read[3] = {
empty_slot_readl,
empty_slot_readl,
empty_slot_readl,
};
static CPUWriteMemoryFunc * const empty_slot_write[3] = {
empty_slot_writel,
empty_slot_writel,
empty_slot_writel,
static const MemoryRegionOps empty_slot_ops = {
.read = empty_slot_read,
.write = empty_slot_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
@ -73,12 +69,10 @@ void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
static int empty_slot_init1(SysBusDevice *dev)
{
EmptySlot *s = FROM_SYSBUS(EmptySlot, dev);
ram_addr_t empty_slot_offset;
empty_slot_offset = cpu_register_io_memory(empty_slot_read,
empty_slot_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->size, empty_slot_offset | IO_MEM_RAM);
memory_region_init_io(&s->iomem, &empty_slot_ops, s,
"empty-slot", s->size);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}

2
hw/escc.c
View File

@ -888,7 +888,7 @@ static int escc_init1(SysBusDevice *dev)
memory_region_init_io(&s->mmio, &escc_mem_ops, s, "escc",
ESCC_SIZE << s->it_shift);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
if (s->chn[0].type == mouse) {
qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,

37
hw/esp.c
View File

@ -45,6 +45,7 @@ typedef struct ESPState ESPState;
struct ESPState {
SysBusDevice busdev;
MemoryRegion iomem;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
qemu_irq irq;
@ -504,7 +505,8 @@ static void esp_gpio_demux(void *opaque, int irq, int level)
}
}
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
static uint64_t esp_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
ESPState *s = opaque;
uint32_t saddr, old_val;
@ -545,7 +547,8 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
return s->rregs[saddr];
}
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void esp_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
ESPState *s = opaque;
uint32_t saddr;
@ -641,7 +644,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->rregs[ESP_RINTR] = 0;
break;
default:
ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
ESP_ERROR("Unhandled ESP command (%2.2x)\n", (unsigned)val);
break;
}
break;
@ -656,22 +659,23 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->rregs[saddr] = val;
break;
default:
ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", (unsigned)val, saddr);
return;
}
s->wregs[saddr] = val;
}
static CPUReadMemoryFunc * const esp_mem_read[3] = {
esp_mem_readb,
NULL,
NULL,
};
static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 4);
}
static CPUWriteMemoryFunc * const esp_mem_write[3] = {
esp_mem_writeb,
NULL,
esp_mem_writeb,
static const MemoryRegionOps esp_mem_ops = {
.read = esp_mem_read,
.write = esp_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.accepts = esp_mem_accepts,
};
static const VMStateDescription vmstate_esp = {
@ -735,14 +739,13 @@ static const struct SCSIBusInfo esp_scsi_info = {
static int esp_init1(SysBusDevice *dev)
{
ESPState *s = FROM_SYSBUS(ESPState, dev);
int esp_io_memory;
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
memory_region_init_io(&s->iomem, &esp_mem_ops, s,
"esp", ESP_REGS << s->it_shift);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);

2
hw/etraxfs_eth.c
View File

@ -604,7 +604,7 @@ static int fs_eth_init(SysBusDevice *dev)
s->dma_in->client.pull = NULL;
memory_region_init_io(&s->mmio, &eth_ops, s, "etraxfs-eth", 0x5c);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf,

2
hw/etraxfs_pic.c
View File

@ -147,7 +147,7 @@ static int etraxfs_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_nmi);
memory_region_init_io(&s->mmio, &pic_ops, s, "etraxfs-pic", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
return 0;
}

2
hw/etraxfs_ser.c
View File

@ -214,7 +214,7 @@ static int etraxfs_ser_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->mmio, &ser_ops, s, "etraxfs-serial", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr)

2
hw/etraxfs_timer.c
View File

@ -323,7 +323,7 @@ static int etraxfs_timer_init(SysBusDevice *dev)
sysbus_init_irq(dev, &t->nmi);
memory_region_init_io(&t->mmio, &timer_ops, t, "etraxfs-timer", 0x5c);
sysbus_init_mmio_region(dev, &t->mmio);
sysbus_init_mmio(dev, &t->mmio);
qemu_register_reset(etraxfs_timer_reset, t);
return 0;
}

58
hw/fdc.c
View File

@ -373,6 +373,7 @@ enum {
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
struct FDCtrl {
MemoryRegion iomem;
qemu_irq irq;
/* Controller state */
QEMUTimer *result_timer;
@ -491,39 +492,32 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
}
}
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
unsigned ize)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
static void fdctrl_write_mem (void *opaque,
target_phys_addr_t reg, uint32_t value)
static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
uint64_t value, unsigned size)
{
fdctrl_write(opaque, (uint32_t)reg, value);
}
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
fdctrl_read_mem,
fdctrl_read_mem,
fdctrl_read_mem,
static const MemoryRegionOps fdctrl_mem_ops = {
.read = fdctrl_read_mem,
.write = fdctrl_write_mem,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
fdctrl_write_mem,
fdctrl_write_mem,
fdctrl_write_mem,
};
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
fdctrl_read_mem,
NULL,
NULL,
};
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
fdctrl_write_mem,
NULL,
NULL,
static const MemoryRegionOps fdctrl_mem_strict_ops = {
.read = fdctrl_read_mem,
.write = fdctrl_write_mem,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static bool fdrive_media_changed_needed(void *opaque)
@ -1914,17 +1908,15 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
{
FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
FDCtrl *fdctrl = &sys->state;
int io;
int ret;
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x08, io);
memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
fdctrl->dma_chann = -1;
qdev_set_legacy_instance_id(&dev->qdev, io, 2);
qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
ret = fdctrl_init_common(fdctrl);
return ret;
@ -1933,17 +1925,15 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
static int sun4m_fdc_init1(SysBusDevice *dev)
{
FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read_strict,
fdctrl_mem_write_strict, fdctrl,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x08, io);
memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
"fdctrl", 0x08);
sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
fdctrl->sun4m = 1;
qdev_set_legacy_instance_id(&dev->qdev, io, 2);
qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
return fdctrl_init_common(fdctrl);
}

108
hw/fw_cfg.c
View File

@ -39,6 +39,7 @@
#endif
#define FW_CFG_SIZE 2
#define FW_CFG_DATA_SIZE 1
typedef struct FWCfgEntry {
uint32_t len;
@ -49,6 +50,7 @@ typedef struct FWCfgEntry {
struct FWCfgState {
SysBusDevice busdev;
MemoryRegion ctl_iomem, data_iomem, comb_iomem;
uint32_t ctl_iobase, data_iobase;
FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
FWCfgFiles *files;
@ -232,60 +234,76 @@ static uint8_t fw_cfg_read(FWCfgState *s)
return ret;
}
static uint32_t fw_cfg_io_readb(void *opaque, uint32_t addr)
static uint64_t fw_cfg_data_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_io_writeb(void *opaque, uint32_t addr, uint32_t value)
static void fw_cfg_data_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
fw_cfg_write(opaque, (uint8_t)value);
}
static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value)
static void fw_cfg_ctl_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
fw_cfg_select(opaque, (uint16_t)value);
}
static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
static bool fw_cfg_ctl_mem_valid(void *opaque, target_phys_addr_t addr,
unsigned size, bool is_write)
{
return is_write && size == 2;
}
static uint64_t fw_cfg_comb_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
fw_cfg_write(opaque, (uint8_t)value);
switch (size) {
case 1:
fw_cfg_write(opaque, (uint8_t)value);
break;
case 2:
fw_cfg_select(opaque, (uint16_t)value);
break;
}
}
static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
static bool fw_cfg_comb_valid(void *opaque, target_phys_addr_t addr,
unsigned size, bool is_write)
{
fw_cfg_select(opaque, (uint16_t)value);
return (size == 1) || (is_write && size == 2);
}
static CPUReadMemoryFunc * const fw_cfg_ctl_mem_read[3] = {
NULL,
NULL,
NULL,
static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
.write = fw_cfg_ctl_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.accepts = fw_cfg_ctl_mem_valid,
};
static CPUWriteMemoryFunc * const fw_cfg_ctl_mem_write[3] = {
NULL,
fw_cfg_mem_writew,
NULL,
static const MemoryRegionOps fw_cfg_data_mem_ops = {
.read = fw_cfg_data_mem_read,
.write = fw_cfg_data_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static CPUReadMemoryFunc * const fw_cfg_data_mem_read[3] = {
fw_cfg_mem_readb,
NULL,
NULL,
};
static CPUWriteMemoryFunc * const fw_cfg_data_mem_write[3] = {
fw_cfg_mem_writeb,
NULL,
NULL,
static const MemoryRegionOps fw_cfg_comb_mem_ops = {
.read = fw_cfg_comb_read,
.write = fw_cfg_comb_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.accepts = fw_cfg_comb_valid,
};
static void fw_cfg_reset(DeviceState *d)
@ -489,24 +507,26 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
static int fw_cfg_init1(SysBusDevice *dev)
{
FWCfgState *s = FROM_SYSBUS(FWCfgState, dev);
int io_ctl_memory, io_data_memory;
io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
fw_cfg_ctl_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_ctl_memory);
memory_region_init_io(&s->ctl_iomem, &fw_cfg_ctl_mem_ops, s,
"fwcfg.ctl", FW_CFG_SIZE);
sysbus_init_mmio(dev, &s->ctl_iomem);
memory_region_init_io(&s->data_iomem, &fw_cfg_data_mem_ops, s,
"fwcfg.data", FW_CFG_DATA_SIZE);
sysbus_init_mmio(dev, &s->data_iomem);
/* In case ctl and data overlap: */
memory_region_init_io(&s->comb_iomem, &fw_cfg_comb_mem_ops, s,
"fwcfg", FW_CFG_SIZE);
io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
fw_cfg_data_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_data_memory);
if (s->ctl_iobase) {
register_ioport_write(s->ctl_iobase, 2, 2, fw_cfg_io_writew, s);
}
if (s->data_iobase) {
register_ioport_read(s->data_iobase, 1, 1, fw_cfg_io_readb, s);
register_ioport_write(s->data_iobase, 1, 1, fw_cfg_io_writeb, s);
if (s->ctl_iobase + 1 == s->data_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->comb_iomem);
} else {
if (s->ctl_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->ctl_iomem);
}
if (s->data_iobase) {
sysbus_add_io(dev, s->data_iobase, &s->data_iomem);
}
}
return 0;
}

4
hw/g364fb.c
View File

@ -540,8 +540,8 @@ static int g364fb_sysbus_init(SysBusDevice *dev)
g364fb_init(&dev->qdev, s);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio_region(dev, &s->mem_ctrl);
sysbus_init_mmio_region(dev, &s->mem_vram);
sysbus_init_mmio(dev, &s->mem_ctrl);
sysbus_init_mmio(dev, &s->mem_vram);
return 0;
}

4
hw/grackle_pci.c
View File

@ -108,8 +108,8 @@ static int pci_grackle_init_device(SysBusDevice *dev)
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-data-idx", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
sysbus_init_mmio(dev, &s->host_state.conf_mem);
sysbus_init_mmio(dev, &s->host_state.data_mem);
qemu_register_reset(pci_grackle_reset, &s->host_state);
return 0;

30
hw/grlib_apbuart.c
View File

@ -67,7 +67,7 @@
typedef struct UART {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
CharDriverState *chr;
@ -103,7 +103,8 @@ static void grlib_apbuart_event(void *opaque, int event)
}
static void
grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
UART *uart = opaque;
unsigned char c = 0;
@ -136,18 +137,21 @@ grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
trace_grlib_apbuart_writel_unknown(addr, value);
}
static CPUReadMemoryFunc * const grlib_apbuart_read[] = {
NULL, NULL, NULL,
};
static bool grlib_apbuart_accepts(void *opaque, target_phys_addr_t addr,
unsigned size, bool is_write)
{
return is_write && size == 4;
}
static CPUWriteMemoryFunc * const grlib_apbuart_write[] = {
NULL, NULL, grlib_apbuart_writel,
static const MemoryRegionOps grlib_apbuart_ops = {
.write = grlib_apbuart_write,
.valid.accepts = grlib_apbuart_accepts,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int grlib_apbuart_init(SysBusDevice *dev)
{
UART *uart = FROM_SYSBUS(typeof(*uart), dev);
int uart_regs = 0;
qemu_chr_add_handlers(uart->chr,
grlib_apbuart_can_receive,
@ -157,14 +161,10 @@ static int grlib_apbuart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &uart->irq);
uart_regs = cpu_register_io_memory(grlib_apbuart_read,
grlib_apbuart_write,
uart, DEVICE_NATIVE_ENDIAN);
if (uart_regs < 0) {
return -1;
}
memory_region_init_io(&uart->iomem, &grlib_apbuart_ops, uart,
"uart", UART_REG_SIZE);
sysbus_init_mmio(dev, UART_REG_SIZE, uart_regs);
sysbus_init_mmio(dev, &uart->iomem);
return 0;
}

34
hw/grlib_gptimer.c
View File

@ -68,6 +68,7 @@ struct GPTimer {
struct GPTimerUnit {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t nr_timers; /* Number of timers available */
uint32_t freq_hz; /* System frequency */
@ -153,7 +154,8 @@ static void grlib_gptimer_hit(void *opaque)
}
}
static uint32_t grlib_gptimer_readl(void *opaque, target_phys_addr_t addr)
static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
GPTimerUnit *unit = opaque;
target_phys_addr_t timer_addr;
@ -211,8 +213,8 @@ static uint32_t grlib_gptimer_readl(void *opaque, target_phys_addr_t addr)
return 0;
}
static void
grlib_gptimer_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
static void grlib_gptimer_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
GPTimerUnit *unit = opaque;
target_phys_addr_t timer_addr;
@ -299,12 +301,14 @@ grlib_gptimer_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
trace_grlib_gptimer_writel(-1, addr, value);
}
static CPUReadMemoryFunc * const grlib_gptimer_read[] = {
NULL, NULL, grlib_gptimer_readl,
};
static CPUWriteMemoryFunc * const grlib_gptimer_write[] = {
NULL, NULL, grlib_gptimer_writel,
static const MemoryRegionOps grlib_gptimer_ops = {
.read = grlib_gptimer_read,
.write = grlib_gptimer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void grlib_gptimer_reset(DeviceState *d)
@ -340,7 +344,6 @@ static int grlib_gptimer_init(SysBusDevice *dev)
{
GPTimerUnit *unit = FROM_SYSBUS(typeof(*unit), dev);
unsigned int i;
int timer_regs;
assert(unit->nr_timers > 0);
assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
@ -361,15 +364,10 @@ static int grlib_gptimer_init(SysBusDevice *dev)
ptimer_set_freq(timer->ptimer, unit->freq_hz);
}
timer_regs = cpu_register_io_memory(grlib_gptimer_read,
grlib_gptimer_write,
unit, DEVICE_NATIVE_ENDIAN);
if (timer_regs < 0) {
return -1;
}
memory_region_init_io(&unit->iomem, &grlib_gptimer_ops, unit, "gptimer",
UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
sysbus_init_mmio(dev, UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers,
timer_regs);
sysbus_init_mmio(dev, &unit->iomem);
return 0;
}

34
hw/grlib_irqmp.c
View File

@ -49,6 +49,7 @@ typedef struct IRQMPState IRQMPState;
typedef struct IRQMP {
SysBusDevice busdev;
MemoryRegion iomem;
void *set_pil_in;
void *set_pil_in_opaque;
@ -161,7 +162,8 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level)
}
}
static uint32_t grlib_irqmp_readl(void *opaque, target_phys_addr_t addr)
static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
IRQMP *irqmp = opaque;
IRQMPState *state;
@ -224,8 +226,8 @@ static uint32_t grlib_irqmp_readl(void *opaque, target_phys_addr_t addr)
return 0;
}
static void
grlib_irqmp_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
IRQMP *irqmp = opaque;
IRQMPState *state;
@ -311,12 +313,14 @@ grlib_irqmp_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
trace_grlib_irqmp_writel_unknown(addr, value);
}
static CPUReadMemoryFunc * const grlib_irqmp_read[] = {
NULL, NULL, &grlib_irqmp_readl,
};
static CPUWriteMemoryFunc * const grlib_irqmp_write[] = {
NULL, NULL, &grlib_irqmp_writel,
static const MemoryRegionOps grlib_irqmp_ops = {
.read = grlib_irqmp_read,
.write = grlib_irqmp_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void grlib_irqmp_reset(DeviceState *d)
@ -332,7 +336,6 @@ static void grlib_irqmp_reset(DeviceState *d)
static int grlib_irqmp_init(SysBusDevice *dev)
{
IRQMP *irqmp = FROM_SYSBUS(typeof(*irqmp), dev);
int irqmp_regs;
assert(irqmp != NULL);
@ -341,17 +344,12 @@ static int grlib_irqmp_init(SysBusDevice *dev)
return -1;
}
irqmp_regs = cpu_register_io_memory(grlib_irqmp_read,
grlib_irqmp_write,
irqmp, DEVICE_NATIVE_ENDIAN);
memory_region_init_io(&irqmp->iomem, &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);
irqmp->state = g_malloc0(sizeof *irqmp->state);
if (irqmp_regs < 0) {
return -1;
}
sysbus_init_mmio(dev, IRQMP_REG_SIZE, irqmp_regs);
sysbus_init_mmio(dev, &irqmp->iomem);
return 0;
}

62
hw/hpet.c
View File

@ -59,6 +59,7 @@ typedef struct HPETTimer { /* timers */
typedef struct HPETState {
SysBusDevice busdev;
MemoryRegion iomem;
uint64_t hpet_offset;
qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
uint32_t flags;
@ -354,7 +355,8 @@ static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
}
#endif
static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
HPETState *s = opaque;
uint64_t cur_tick, index;
@ -425,24 +427,8 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
return 0;
}
#ifdef HPET_DEBUG
static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
addr, value);
}
static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
addr, value);
}
#endif
static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
int i;
HPETState *s = opaque;
@ -450,7 +436,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
index = addr;
old_val = hpet_ram_readl(opaque, addr);
old_val = hpet_ram_read(opaque, addr, 4);
new_val = value;
/*address range of all TN regs*/
@ -605,26 +591,14 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const hpet_ram_read[] = {
#ifdef HPET_DEBUG
hpet_ram_readb,
hpet_ram_readw,
#else
NULL,
NULL,
#endif
hpet_ram_readl,
};
static CPUWriteMemoryFunc * const hpet_ram_write[] = {
#ifdef HPET_DEBUG
hpet_ram_writeb,
hpet_ram_writew,
#else
NULL,
NULL,
#endif
hpet_ram_writel,
static const MemoryRegionOps hpet_ram_ops = {
.read = hpet_ram_read,
.write = hpet_ram_write,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void hpet_reset(DeviceState *d)
@ -677,7 +651,7 @@ static void hpet_handle_rtc_irq(void *opaque, int n, int level)
static int hpet_init(SysBusDevice *dev)
{
HPETState *s = FROM_SYSBUS(HPETState, dev);
int i, iomemtype;
int i;
HPETTimer *timer;
if (hpet_cfg.count == UINT8_MAX) {
@ -716,10 +690,8 @@ static int hpet_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
/* HPET Area */
iomemtype = cpu_register_io_memory(hpet_ram_read,
hpet_ram_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x400, iomemtype);
memory_region_init_io(&s->iomem, &hpet_ram_ops, s, "hpet", 0x400);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}

2
hw/ide.h
View File

@ -3,6 +3,7 @@
#include "isa.h"
#include "pci.h"
#include "memory.h"
#define MAX_IDE_DEVS 2
@ -24,6 +25,7 @@ MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
/* ide-mmio.c */
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);

57
hw/ide/mmio.c
View File

@ -37,6 +37,7 @@
typedef struct {
IDEBus bus;
int shift;
MemoryRegion iomem1, iomem2;
} MMIOState;
static void mmio_ide_reset(void *opaque)
@ -46,7 +47,8 @@ static void mmio_ide_reset(void *opaque)
ide_bus_reset(&s->bus);
}
static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
MMIOState *s = opaque;
addr >>= s->shift;
@ -56,8 +58,8 @@ static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
return ide_data_readw(&s->bus, 0);
}
static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
addr >>= s->shift;
@ -67,41 +69,30 @@ static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
ide_data_writew(&s->bus, 0, val);
}
static CPUReadMemoryFunc * const mmio_ide_reads[] = {
mmio_ide_read,
mmio_ide_read,
mmio_ide_read,
static const MemoryRegionOps mmio_ide_ops = {
.read = mmio_ide_read,
.write = mmio_ide_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
mmio_ide_write,
mmio_ide_write,
mmio_ide_write,
};
static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
static uint64_t mmio_ide_status_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
MMIOState *s= opaque;
return ide_status_read(&s->bus, 0);
}
static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
ide_cmd_write(&s->bus, 0, val);
}
static CPUReadMemoryFunc * const mmio_ide_status[] = {
mmio_ide_status_read,
mmio_ide_status_read,
mmio_ide_status_read,
};
static CPUWriteMemoryFunc * const mmio_ide_cmd[] = {
mmio_ide_cmd_write,
mmio_ide_cmd_write,
mmio_ide_cmd_write,
static const MemoryRegionOps mmio_ide_cs_ops = {
.read = mmio_ide_status_read,
.write = mmio_ide_cmd_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_ide_mmio = {
@ -117,22 +108,22 @@ static const VMStateDescription vmstate_ide_mmio = {
};
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
{
MMIOState *s = g_malloc0(sizeof(MMIOState));
int mem1, mem2;
ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq);
s->shift = shift;
mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s,
DEVICE_NATIVE_ENDIAN);
mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(membase, 16 << shift, mem1);
cpu_register_physical_memory(membase2, 2 << shift, mem2);
memory_region_init_io(&s->iomem1, &mmio_ide_ops, s,
"ide-mmio.1", 16 << shift);
memory_region_init_io(&s->iomem2, &mmio_ide_cs_ops, s,
"ide-mmio.2", 2 << shift);
memory_region_add_subregion(address_space, membase, &s->iomem1);
memory_region_add_subregion(address_space, membase2, &s->iomem2);
vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
qemu_register_reset(mmio_ide_reset, s);
}

89
hw/integratorcp.c
View File

@ -18,6 +18,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t memsz;
MemoryRegion flash;
bool flash_mapped;
@ -39,7 +40,8 @@ static uint8_t integrator_spd[128] = {
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
if (offset >= 0x100 && offset < 0x200) {
@ -152,7 +154,7 @@ static void integratorcm_update(integratorcm_state *s)
}
static void integratorcm_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
switch (offset >> 2) {
@ -228,21 +230,14 @@ static void integratorcm_write(void *opaque, target_phys_addr_t offset,
/* Integrator/CM control registers. */
static CPUReadMemoryFunc * const integratorcm_readfn[] = {
integratorcm_read,
integratorcm_read,
integratorcm_read
};
static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
integratorcm_write,
integratorcm_write,
integratorcm_write
static const MemoryRegionOps integratorcm_ops = {
.read = integratorcm_read,
.write = integratorcm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int integratorcm_init(SysBusDevice *dev)
{
int iomemtype;
integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
s->cm_osc = 0x01000048;
@ -269,10 +264,10 @@ static int integratorcm_init(SysBusDevice *dev)
memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
s->flash_mapped = false;
iomemtype = cpu_register_io_memory(integratorcm_readfn,
integratorcm_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
memory_region_init_io(&s->iomem, &integratorcm_ops, s,
"integratorcm", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
integratorcm_do_remap(s, 1);
/* ??? Save/restore. */
return 0;
@ -284,6 +279,7 @@ static int integratorcm_init(SysBusDevice *dev)
typedef struct icp_pic_state
{
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
@ -311,7 +307,8 @@ static void icp_pic_set_irq(void *opaque, int irq, int level)
icp_pic_update(s);
}
static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@ -340,7 +337,7 @@ static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
}
static void icp_pic_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@ -376,35 +373,28 @@ static void icp_pic_write(void *opaque, target_phys_addr_t offset,
icp_pic_update(s);
}
static CPUReadMemoryFunc * const icp_pic_readfn[] = {
icp_pic_read,
icp_pic_read,
icp_pic_read
};
static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
icp_pic_write,
icp_pic_write,
icp_pic_write
static const MemoryRegionOps icp_pic_ops = {
.read = icp_pic_read,
.write = icp_pic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pic_init(SysBusDevice *dev)
{
icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
int iomemtype;
qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_fiq);
iomemtype = cpu_register_io_memory(icp_pic_readfn,
icp_pic_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
/* CP control registers. */
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
@ -422,7 +412,7 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
}
static void icp_control_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
switch (offset >> 2) {
case 1: /* CP_FLASHPROG */
@ -434,26 +424,21 @@ static void icp_control_write(void *opaque, target_phys_addr_t offset,
hw_error("icp_control_write: Bad offset %x\n", (int)offset);
}
}
static CPUReadMemoryFunc * const icp_control_readfn[] = {
icp_control_read,
icp_control_read,
icp_control_read
static const MemoryRegionOps icp_control_ops = {
.read = icp_control_read,
.write = icp_control_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const icp_control_writefn[] = {
icp_control_write,
icp_control_write,
icp_control_write
};
static void icp_control_init(uint32_t base)
static void icp_control_init(target_phys_addr_t base)
{
int iomemtype;
MemoryRegion *io;
iomemtype = cpu_register_io_memory(icp_control_readfn,
icp_control_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00800000, iomemtype);
io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
memory_region_init_io(io, &icp_control_ops, NULL,
"control", 0x00800000);
memory_region_add_subregion(get_system_memory(), base, io);
/* ??? Save/restore. */
}

34
hw/ioapic.c
View File

@ -86,6 +86,7 @@ typedef struct IOAPICState IOAPICState;
struct IOAPICState {
SysBusDevice busdev;
MemoryRegion io_memory;
uint8_t id;
uint8_t ioregsel;
uint32_t irr;
@ -195,7 +196,8 @@ void ioapic_eoi_broadcast(int vector)
}
}
static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
static uint64_t
ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
IOAPICState *s = opaque;
int index;
@ -206,6 +208,9 @@ static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
val = s->ioregsel;
break;
case IOAPIC_IOWIN:
if (size != 4) {
break;
}
switch (s->ioregsel) {
case IOAPIC_REG_ID:
val = s->id << IOAPIC_ID_SHIFT;
@ -234,7 +239,8 @@ static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
}
static void
ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
unsigned int size)
{
IOAPICState *s = opaque;
int index;
@ -244,6 +250,9 @@ ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
s->ioregsel = val;
break;
case IOAPIC_IOWIN:
if (size != 4) {
break;
}
DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
switch (s->ioregsel) {
case IOAPIC_REG_ID:
@ -309,32 +318,23 @@ static void ioapic_reset(DeviceState *d)
}
}
static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
ioapic_mem_readl,
ioapic_mem_readl,
ioapic_mem_readl,
};
static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
ioapic_mem_writel,
ioapic_mem_writel,
ioapic_mem_writel,
static const MemoryRegionOps ioapic_io_ops = {
.read = ioapic_mem_read,
.write = ioapic_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int ioapic_init1(SysBusDevice *dev)
{
IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
int io_memory;
static int ioapic_no;
if (ioapic_no >= MAX_IOAPICS) {
return -1;
}
io_memory = cpu_register_io_memory(ioapic_mem_read,
ioapic_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, io_memory);
memory_region_init_io(&s->io_memory, &ioapic_io_ops, s, "ioapic", 0x1000);
sysbus_init_mmio(dev, &s->io_memory);
qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);

25
hw/jazz_led.c
View File

@ -43,6 +43,7 @@ typedef enum {
} screen_state_t;
typedef struct LedState {
MemoryRegion iomem;
uint8_t segments;
DisplayState *ds;
screen_state_t state;
@ -140,16 +141,12 @@ static void led_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
#endif
}
static CPUReadMemoryFunc * const led_read[3] = {
led_readb,
led_readw,
led_readl,
};
static CPUWriteMemoryFunc * const led_write[3] = {
led_writeb,
led_writew,
led_writel,
static const MemoryRegionOps led_ops = {
.old_mmio = {
.read = { led_readb, led_readw, led_readl, },
.write = { led_writeb, led_writew, led_writel, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
/***********************************************************/
@ -307,18 +304,16 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
dpy_update(s->ds, 0, 0, 2, 1);
}
void jazz_led_init(target_phys_addr_t base)
void jazz_led_init(MemoryRegion *address_space, target_phys_addr_t base)
{
LedState *s;
int io;
s = g_malloc0(sizeof(LedState));
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
io = cpu_register_io_memory(led_read, led_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 1, io);
memory_region_init_io(&s->iomem, &led_ops, s, "led", 1);
memory_region_add_subregion(address_space, base, &s->iomem);
s->ds = graphic_console_init(jazz_led_update_display,
jazz_led_invalidate_display,

2
hw/lan9118.c
View File

@ -1132,7 +1132,7 @@ static int lan9118_init1(SysBusDevice *dev)
int i;
memory_region_init_io(&s->mmio, &lan9118_mem_ops, s, "lan9118-mmio", 0x100);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);

2
hw/lance.c
View File

@ -121,7 +121,7 @@ static int lance_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);

28
hw/lm32_sys.c
View File

@ -47,6 +47,7 @@ enum {
struct LM32SysState {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t base;
uint32_t regs[R_MAX];
uint8_t testname[MAX_TESTNAME_LEN];
@ -60,7 +61,8 @@ static void copy_testname(LM32SysState *s)
s->testname[MAX_TESTNAME_LEN - 1] = '\0';
}
static void sys_write(void *opaque, target_phys_addr_t addr, uint32_t value)
static void sys_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
LM32SysState *s = opaque;
char *testname;
@ -89,16 +91,16 @@ static void sys_write(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static CPUReadMemoryFunc * const sys_read_fn[] = {
NULL,
NULL,
NULL,
};
static bool sys_ops_accepts(void *opaque, target_phys_addr_t addr,
unsigned size, bool is_write)
{
return is_write && size == 4;
}
static CPUWriteMemoryFunc * const sys_write_fn[] = {
NULL,
NULL,
&sys_write,
static const MemoryRegionOps sys_ops = {
.write = sys_write,
.valid.accepts = sys_ops_accepts,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void sys_reset(DeviceState *d)
@ -115,11 +117,9 @@ static void sys_reset(DeviceState *d)
static int lm32_sys_init(SysBusDevice *dev)
{
LM32SysState *s = FROM_SYSBUS(typeof(*s), dev);
int sys_regs;
sys_regs = cpu_register_io_memory(sys_read_fn, sys_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, sys_regs);
memory_region_init_io(&s->iomem, &sys_ops , s, "sys", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
/* Note: This device is not created in the board initialization,
* instead it has to be added with the -device parameter. Therefore,

30
hw/lm32_timer.c
View File

@ -51,6 +51,7 @@ enum {
struct LM32TimerState {
SysBusDevice busdev;
MemoryRegion iomem;
QEMUBH *bh;
ptimer_state *ptimer;
@ -70,7 +71,7 @@ static void timer_update_irq(LM32TimerState *s)
qemu_set_irq(s->irq, state);
}
static uint32_t timer_read(void *opaque, target_phys_addr_t addr)
static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
LM32TimerState *s = opaque;
uint32_t r = 0;
@ -95,7 +96,8 @@ static uint32_t timer_read(void *opaque, target_phys_addr_t addr)
return r;
}
static void timer_write(void *opaque, target_phys_addr_t addr, uint32_t value)
static void timer_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
LM32TimerState *s = opaque;
@ -131,16 +133,14 @@ static void timer_write(void *opaque, target_phys_addr_t addr, uint32_t value)
timer_update_irq(s);
}
static CPUReadMemoryFunc * const timer_read_fn[] = {
NULL,
NULL,
&timer_read,
};
static CPUWriteMemoryFunc * const timer_write_fn[] = {
NULL,
NULL,
&timer_write,
static const MemoryRegionOps timer_ops = {
.read = timer_read,
.write = timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void timer_hit(void *opaque)
@ -172,7 +172,6 @@ static void timer_reset(DeviceState *d)
static int lm32_timer_init(SysBusDevice *dev)
{
LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
int timer_regs;
sysbus_init_irq(dev, &s->irq);
@ -180,9 +179,8 @@ static int lm32_timer_init(SysBusDevice *dev)
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->freq_hz);
timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, timer_regs);
memory_region_init_io(&s->iomem, &timer_ops, s, "timer", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}

31
hw/lm32_uart.c
View File

@ -91,6 +91,7 @@ enum {
struct LM32UartState {
SysBusDevice busdev;
MemoryRegion iomem;
CharDriverState *chr;
qemu_irq irq;
@ -124,7 +125,8 @@ static void uart_update_irq(LM32UartState *s)
qemu_set_irq(s->irq, irq);
}
static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
LM32UartState *s = opaque;
uint32_t r = 0;
@ -158,7 +160,8 @@ static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
return r;
}
static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
static void uart_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
LM32UartState *s = opaque;
unsigned char ch = value;
@ -192,16 +195,14 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
uart_update_irq(s);
}
static CPUReadMemoryFunc * const uart_read_fn[] = {
NULL,
NULL,
&uart_read,
};
static CPUWriteMemoryFunc * const uart_write_fn[] = {
NULL,
NULL,
&uart_write,
static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
@ -245,13 +246,11 @@ static void uart_reset(DeviceState *d)
static int lm32_uart_init(SysBusDevice *dev)
{
LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
int uart_regs;
sysbus_init_irq(dev, &s->irq);
uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr) {

23
hw/m48t59.c
View File

@ -52,6 +52,7 @@
struct M48t59State {
/* Hardware parameters */
qemu_irq IRQ;
MemoryRegion iomem;
uint32_t io_base;
uint32_t size;
/* RTC management */
@ -573,16 +574,12 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
return retval;
}
static CPUWriteMemoryFunc * const nvram_write[] = {
&nvram_writeb,
&nvram_writew,
&nvram_writel,
};
static CPUReadMemoryFunc * const nvram_read[] = {
&nvram_readb,
&nvram_readw,
&nvram_readl,
static const MemoryRegionOps nvram_ops = {
.old_mmio = {
.read = { nvram_readb, nvram_readw, nvram_readl, },
.write = { nvram_writeb, nvram_writew, nvram_writel, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_m48t59 = {
@ -712,13 +709,11 @@ static int m48t59_init1(SysBusDevice *dev)
{
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
M48t59State *s = &d->state;
int mem_index;
sysbus_init_irq(dev, &s->IRQ);
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->size, mem_index);
memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size);
sysbus_init_mmio(dev, &s->iomem);
m48t59_init_common(s);
return 0;

28
hw/marvell_88w8618_audio.c
View File

@ -36,6 +36,7 @@
typedef struct mv88w8618_audio_state {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
uint32_t playback_mode;
uint32_t status;
@ -134,7 +135,8 @@ static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s)
wm8750_set_bclk_in(s->wm, rate);
}
static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset)
static uint64_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
mv88w8618_audio_state *s = opaque;
@ -160,7 +162,7 @@ static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
mv88w8618_audio_state *s = opaque;
@ -227,31 +229,23 @@ static void mv88w8618_audio_reset(DeviceState *d)
s->phys_buf = 0;
}
static CPUReadMemoryFunc * const mv88w8618_audio_readfn[] = {
mv88w8618_audio_read,
mv88w8618_audio_read,
mv88w8618_audio_read
};
static CPUWriteMemoryFunc * const mv88w8618_audio_writefn[] = {
mv88w8618_audio_write,
mv88w8618_audio_write,
mv88w8618_audio_write
static const MemoryRegionOps mv88w8618_audio_ops = {
.read = mv88w8618_audio_read,
.write = mv88w8618_audio_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_audio_init(SysBusDevice *dev)
{
mv88w8618_audio_state *s = FROM_SYSBUS(mv88w8618_audio_state, dev);
int iomemtype;
sysbus_init_irq(dev, &s->irq);
wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s);
iomemtype = cpu_register_io_memory(mv88w8618_audio_readfn,
mv88w8618_audio_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_AUDIO_SIZE, iomemtype);
memory_region_init_io(&s->iomem, &mv88w8618_audio_ops, s,
"audio", MP_AUDIO_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}

23
hw/mcf.h
View File

@ -2,20 +2,29 @@
#define HW_MCF_H
/* Motorola ColdFire device prototypes. */
struct MemoryRegion;
/* mcf_uart.c */
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
unsigned size);
void mcf_uart_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
CharDriverState *chr);
void mcf_uart_mm_init(struct MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq, CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
target_phys_addr_t base,
CPUState *env);
/* mcf_fec.c */
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
target_phys_addr_t base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
uint32_t base, CPUState *env);
#endif

62
hw/mcf5206.c
View File

@ -9,6 +9,7 @@
#include "mcf.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "exec-memory.h"
/* General purpose timer module. */
typedef struct {
@ -144,6 +145,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq)
typedef struct {
CPUState *env;
MemoryRegion iomem;
m5206_timer_state *timer[2];
void *uart[2];
uint8_t scr;
@ -261,16 +263,17 @@ static void m5206_mbar_reset(m5206_mbar_state *s)
s->par = 0;
}
static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
static uint64_t m5206_mbar_read(m5206_mbar_state *s,
uint64_t offset, unsigned size)
{
if (offset >= 0x100 && offset < 0x120) {
return m5206_timer_read(s->timer[0], offset - 0x100);
} else if (offset >= 0x120 && offset < 0x140) {
return m5206_timer_read(s->timer[1], offset - 0x120);
} else if (offset >= 0x140 && offset < 0x160) {
return mcf_uart_read(s->uart[0], offset - 0x140);
return mcf_uart_read(s->uart[0], offset - 0x140, size);
} else if (offset >= 0x180 && offset < 0x1a0) {
return mcf_uart_read(s->uart[1], offset - 0x180);
return mcf_uart_read(s->uart[1], offset - 0x180, size);
}
switch (offset) {
case 0x03: return s->scr;
@ -299,7 +302,7 @@ static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
}
static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
if (offset >= 0x100 && offset < 0x120) {
m5206_timer_write(s->timer[0], offset - 0x100, value);
@ -308,10 +311,10 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
m5206_timer_write(s->timer[1], offset - 0x120, value);
return;
} else if (offset >= 0x140 && offset < 0x160) {
mcf_uart_write(s->uart[0], offset - 0x140, value);
mcf_uart_write(s->uart[0], offset - 0x140, value, size);
return;
} else if (offset >= 0x180 && offset < 0x1a0) {
mcf_uart_write(s->uart[1], offset - 0x180, value);
mcf_uart_write(s->uart[1], offset - 0x180, value, size);
return;
}
switch (offset) {
@ -385,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
}
return val & 0xff;
}
return m5206_mbar_read(s, offset);
return m5206_mbar_read(s, offset, 1);
}
static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
@ -409,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
val |= m5206_mbar_readb(opaque, offset + 1);
return val;
}
return m5206_mbar_read(s, offset);
return m5206_mbar_read(s, offset, 2);
}
static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
@ -427,7 +430,7 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
val |= m5206_mbar_readw(opaque, offset + 2);
return val;
}
return m5206_mbar_read(s, offset);
return m5206_mbar_read(s, offset, 4);
}
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
@ -456,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
m5206_mbar_writew(opaque, offset & ~1, tmp);
return;
}
m5206_mbar_write(s, offset, value);
m5206_mbar_write(s, offset, value, 1);
}
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
@ -484,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
m5206_mbar_writeb(opaque, offset + 1, value & 0xff);
return;
}
m5206_mbar_write(s, offset, value);
m5206_mbar_write(s, offset, value, 2);
}
static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
@ -502,32 +505,35 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
m5206_mbar_writew(opaque, offset + 2, value & 0xffff);
return;
}
m5206_mbar_write(s, offset, value);
m5206_mbar_write(s, offset, value, 4);
}
static CPUReadMemoryFunc * const m5206_mbar_readfn[] = {
m5206_mbar_readb,
m5206_mbar_readw,
m5206_mbar_readl
static const MemoryRegionOps m5206_mbar_ops = {
.old_mmio = {
.read = {
m5206_mbar_readb,
m5206_mbar_readw,
m5206_mbar_readl,
},
.write = {
m5206_mbar_writeb,
m5206_mbar_writew,
m5206_mbar_writel,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const m5206_mbar_writefn[] = {
m5206_mbar_writeb,
m5206_mbar_writew,
m5206_mbar_writel
};
qemu_irq *mcf5206_init(uint32_t base, CPUState *env)
qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUState *env)
{
m5206_mbar_state *s;
qemu_irq *pic;
int iomemtype;
s = (m5206_mbar_state *)g_malloc0(sizeof(m5206_mbar_state));
iomemtype = cpu_register_io_memory(m5206_mbar_readfn,
m5206_mbar_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
memory_region_init_io(&s->iomem, &m5206_mbar_ops, s,
"mbar", 0x00001000);
memory_region_add_subregion(sysmem, base, &s->iomem);
pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
s->timer[0] = m5206_timer_init(pic[9]);

11
hw/mcf5208.c
View File

@ -221,11 +221,11 @@ static void mcf5208evb_init(ram_addr_t ram_size,
memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */
pic = mcf_intc_init(0xfc048000, env);
pic = mcf_intc_init(address_space_mem, 0xfc048000, env);
mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);
mcf5208_sys_init(address_space_mem, pic);
@ -234,7 +234,8 @@ static void mcf5208evb_init(ram_addr_t ram_size,
exit(1);
}
if (nd_table[0].vlan)
mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
mcf_fec_init(address_space_mem, &nd_table[0],
0xfc030000, pic + 36);
/* 0xfc000000 SCM. */
/* 0xfc004000 XBS. */

38
hw/mcf_fec.c
View File

@ -10,6 +10,7 @@
#include "mcf.h"
/* For crc32 */
#include <zlib.h>
#include "exec-memory.h"
//#define DEBUG_FEC 1
@ -23,8 +24,9 @@ do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
#define FEC_MAX_FRAME_SIZE 2032
typedef struct {
MemoryRegion *sysmem;
MemoryRegion iomem;
qemu_irq *irq;
int mmio_index;
NICState *nic;
NICConf conf;
uint32_t irq_state;
@ -214,7 +216,8 @@ static void mcf_fec_reset(mcf_fec_state *s)
s->rfsr = 0x500;
}
static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
static uint64_t mcf_fec_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@ -251,7 +254,8 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
}
}
static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
static void mcf_fec_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@ -429,23 +433,18 @@ static ssize_t mcf_fec_receive(VLANClientState *nc, const uint8_t *buf, size_t s
return size;
}
static CPUReadMemoryFunc * const mcf_fec_readfn[] = {
mcf_fec_read,
mcf_fec_read,
mcf_fec_read
};
static CPUWriteMemoryFunc * const mcf_fec_writefn[] = {
mcf_fec_write,
mcf_fec_write,
mcf_fec_write
static const MemoryRegionOps mcf_fec_ops = {
.read = mcf_fec_read,
.write = mcf_fec_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void mcf_fec_cleanup(VLANClientState *nc)
{
mcf_fec_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
cpu_unregister_io_memory(s->mmio_index);
memory_region_del_subregion(s->sysmem, &s->iomem);
memory_region_destroy(&s->iomem);
g_free(s);
}
@ -458,18 +457,19 @@ static NetClientInfo net_mcf_fec_info = {
.cleanup = mcf_fec_cleanup,
};
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd,
target_phys_addr_t base, qemu_irq *irq)
{
mcf_fec_state *s;
qemu_check_nic_model(nd, "mcf_fec");
s = (mcf_fec_state *)g_malloc0(sizeof(mcf_fec_state));
s->sysmem = sysmem;
s->irq = irq;
s->mmio_index = cpu_register_io_memory(mcf_fec_readfn,
mcf_fec_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x400, s->mmio_index);
memory_region_init_io(&s->iomem, &mcf_fec_ops, s, "fec", 0x400);
memory_region_add_subregion(sysmem, base, &s->iomem);
s->conf.macaddr = nd->macaddr;
s->conf.vlan = nd->vlan;

33
hw/mcf_intc.c
View File

@ -7,8 +7,10 @@
*/
#include "hw.h"
#include "mcf.h"
#include "exec-memory.h"
typedef struct {
MemoryRegion iomem;
uint64_t ipr;
uint64_t imr;
uint64_t ifr;
@ -41,7 +43,8 @@ static void mcf_intc_update(mcf_intc_state *s)
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
static uint64_t mcf_intc_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@ -73,7 +76,8 @@ static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
}
}
static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
static void mcf_intc_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@ -127,31 +131,24 @@ static void mcf_intc_reset(mcf_intc_state *s)
s->active_vector = 24;
}
static CPUReadMemoryFunc * const mcf_intc_readfn[] = {
mcf_intc_read,
mcf_intc_read,
mcf_intc_read
static const MemoryRegionOps mcf_intc_ops = {
.read = mcf_intc_read,
.write = mcf_intc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const mcf_intc_writefn[] = {
mcf_intc_write,
mcf_intc_write,
mcf_intc_write
};
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
target_phys_addr_t base,
CPUState *env)
{
mcf_intc_state *s;
int iomemtype;
s = g_malloc0(sizeof(mcf_intc_state));
s->env = env;
mcf_intc_reset(s);
iomemtype = cpu_register_io_memory(mcf_intc_readfn,
mcf_intc_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
memory_region_init_io(&s->iomem, &mcf_intc_ops, s, "mcf", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
}

34
hw/mcf_uart.c
View File

@ -8,8 +8,10 @@
#include "hw.h"
#include "mcf.h"
#include "qemu-char.h"
#include "exec-memory.h"
typedef struct {
MemoryRegion iomem;
uint8_t mr[2];
uint8_t sr;
uint8_t isr;
@ -64,7 +66,8 @@ static void mcf_uart_update(mcf_uart_state *s)
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@ -182,7 +185,8 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
}
}
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
void mcf_uart_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@ -283,28 +287,20 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
return s;
}
static CPUReadMemoryFunc * const mcf_uart_readfn[] = {
mcf_uart_read,
mcf_uart_read,
mcf_uart_read
static const MemoryRegionOps mcf_uart_ops = {
.read = mcf_uart_read,
.write = mcf_uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
mcf_uart_write,
mcf_uart_write,
mcf_uart_write
};
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
void mcf_uart_mm_init(MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq,
CharDriverState *chr)
{
mcf_uart_state *s;
int iomemtype;
s = mcf_uart_init(irq, chr);
iomemtype = cpu_register_io_memory(mcf_uart_readfn,
mcf_uart_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40, iomemtype);
memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40);
memory_region_add_subregion(sysmem, base, &s->iomem);
}

2
hw/milkymist-ac97.c
View File

@ -302,7 +302,7 @@ static int milkymist_ac97_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &ac97_mmio_ops, s,
"milkymist-ac97", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}

2
hw/milkymist-hpdmc.c
View File

@ -129,7 +129,7 @@ static int milkymist_hpdmc_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &hpdmc_mmio_ops, s,
"milkymist-hpdmc", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}

2
hw/milkymist-memcard.c
View File

@ -255,7 +255,7 @@ static int milkymist_memcard_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &memcard_mmio_ops, s,
"milkymist-memcard", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}

2
hw/milkymist-minimac2.c
View File

@ -465,7 +465,7 @@ static int milkymist_minimac2_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &minimac2_ops, s,
"milkymist-minimac2", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
/* register buffers memory */
memory_region_init_ram(&s->buffers, NULL, "milkymist-minimac2.buffers",

2
hw/milkymist-pfpu.c
View File

@ -499,7 +499,7 @@ static int milkymist_pfpu_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &pfpu_mmio_ops, s,
"milkymist-pfpu", MICROCODE_END * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}

2
hw/milkymist-softusb.c
View File

@ -264,7 +264,7 @@ static int milkymist_softusb_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &softusb_mmio_ops, s,
"milkymist-softusb", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
/* register pmem and dmem */
memory_region_init_ram(&s->pmem, NULL, "milkymist-softusb.pmem",

2
hw/milkymist-sysctl.c
View File

@ -273,7 +273,7 @@ static int milkymist_sysctl_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &sysctl_mmio_ops, s,
"milkymist-sysctl", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}

2
hw/milkymist-tmu2.c
View File

@ -449,7 +449,7 @@ static int milkymist_tmu2_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &tmu2_mmio_ops, s,
"milkymist-tmu2", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}

2
hw/milkymist-uart.c
View File

@ -197,7 +197,7 @@ static int milkymist_uart_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
"milkymist-uart", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr) {

2
hw/milkymist-vgafb.c
View File

@ -272,7 +272,7 @@ static int milkymist_vgafb_init(SysBusDevice *dev)
memory_region_init_io(&s->regs_region, &vgafb_mmio_ops, s,
"milkymist-vgafb", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
sysbus_init_mmio(dev, &s->regs_region);
s->ds = graphic_console_init(vgafb_update_display,
vgafb_invalidate_display,

8
hw/mips.h
View File

@ -2,6 +2,8 @@
#define HW_MIPS_H
/* Definitions for mips board emulation. */
#include "memory.h"
/* gt64xxx.c */
PCIBus *gt64120_register(qemu_irq *pic);
@ -9,7 +11,7 @@ PCIBus *gt64120_register(qemu_irq *pic);
PCIBus *bonito_init(qemu_irq *pic);
/* jazz_led.c */
void jazz_led_init(target_phys_addr_t base);
void jazz_led_init(MemoryRegion *address_space, target_phys_addr_t base);
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
@ -18,10 +20,12 @@ void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
qemu_irq **irqs, rc4030_dma **dmas);
qemu_irq **irqs, rc4030_dma **dmas,
MemoryRegion *sysmem);
/* dp8393x.c */
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));

10
hw/mips_jazz.c
View File

@ -177,7 +177,8 @@ static void mips_jazz_init(MemoryRegion *address_space,
cpu_mips_clock_init(env);
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
address_space);
memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
@ -226,7 +227,7 @@ static void mips_jazz_init(MemoryRegion *address_space,
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
dp83932_init(nd, 0x80001000, 2, rc4030[4],
dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
rc4030_opaque, rc4030_dma_memory_rw);
break;
} else if (strcmp(nd->model, "?") == 0) {
@ -274,7 +275,8 @@ static void mips_jazz_init(MemoryRegion *address_space,
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
parallel_hds[0]);
/* Sound card */
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
@ -287,7 +289,7 @@ static void mips_jazz_init(MemoryRegion *address_space,
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
jazz_led_init(0x8000f000);
jazz_led_init(address_space, 0x8000f000);
}
static

2
hw/mipsnet.c
View File

@ -236,7 +236,7 @@ static int mipsnet_sysbus_init(SysBusDevice *dev)
MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev, dev);
memory_region_init_io(&s->io, &mipsnet_ioport_ops, s, "mipsnet-io", 36);
sysbus_init_mmio_region(dev, &s->io);
sysbus_init_mmio(dev, &s->io);
sysbus_init_irq(dev, &s->irq);
s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,

35
hw/mpc8544_guts.c
View File

@ -53,11 +53,13 @@
struct GutsState {
SysBusDevice busdev;
MemoryRegion iomem;
};
typedef struct GutsState GutsState;
static uint32_t mpc8544_guts_read32(void *opaque, target_phys_addr_t addr)
static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t value = 0;
CPUState *env = cpu_single_env;
@ -78,14 +80,8 @@ static uint32_t mpc8544_guts_read32(void *opaque, target_phys_addr_t addr)
return value;
}
static CPUReadMemoryFunc * const mpc8544_guts_read[] = {
NULL,
NULL,
&mpc8544_guts_read32,
};
static void mpc8544_guts_write32(void *opaque, target_phys_addr_t addr,
uint32_t value)
static void mpc8544_guts_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
@ -97,27 +93,30 @@ static void mpc8544_guts_write32(void *opaque, target_phys_addr_t addr,
break;
default:
fprintf(stderr, "guts: Unknown register write: %x = %x\n",
(int)addr, value);
(int)addr, (unsigned)value);
break;
}
}
static CPUWriteMemoryFunc * const mpc8544_guts_write[] = {
NULL,
NULL,
&mpc8544_guts_write32,
static const MemoryRegionOps mpc8544_guts_ops = {
.read = mpc8544_guts_read,
.write = mpc8544_guts_write,
.endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static int mpc8544_guts_initfn(SysBusDevice *dev)
{
GutsState *s;
int iomem;
s = FROM_SYSBUS(GutsState, sysbus_from_qdev(dev));
iomem = cpu_register_io_memory(mpc8544_guts_read, mpc8544_guts_write, s,
DEVICE_BIG_ENDIAN);
sysbus_init_mmio(dev, MPC8544_GUTS_MMIO_SIZE, iomem);
memory_region_init_io(&s->iomem, &mpc8544_guts_ops, s,
"mpc6544.guts", MPC8544_GUTS_MMIO_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}

2
hw/mpcore.c
View File

@ -275,7 +275,7 @@ static int mpcore_priv_init(SysBusDevice *dev)
gic_init(&s->gic, s->num_cpu);
mpcore_priv_map_setup(s);
sysbus_init_mmio_region(dev, &s->container);
sysbus_init_mmio(dev, &s->container);
for (i = 0; i < s->num_cpu * 2; i++) {
mpcore_timer_init(s, &s->timer[i], i);
}

29
hw/mst_fpga.c
View File

@ -34,6 +34,7 @@
typedef struct mst_irq_state{
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq parent;
@ -86,8 +87,8 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
}
static uint32_t
mst_fpga_readb(void *opaque, target_phys_addr_t addr)
static uint64_t
mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
@ -124,7 +125,8 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr)
}
static void
mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
value &= 0xffffffff;
@ -175,17 +177,11 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
mst_fpga_readb,
mst_fpga_readb,
mst_fpga_readb,
static const MemoryRegionOps mst_fpga_ops = {
.read = mst_fpga_readb,
.write = mst_fpga_writeb,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
mst_fpga_writeb,
mst_fpga_writeb,
mst_fpga_writeb,
};
static int mst_fpga_post_load(void *opaque, int version_id)
{
@ -198,7 +194,6 @@ static int mst_fpga_post_load(void *opaque, int version_id)
static int mst_fpga_init(SysBusDevice *dev)
{
mst_irq_state *s;
int iomemtype;
s = FROM_SYSBUS(mst_irq_state, dev);
@ -210,9 +205,9 @@ static int mst_fpga_init(SysBusDevice *dev)
/* alloc the external 16 irqs */
qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
iomemtype = cpu_register_io_memory(mst_fpga_readfn,
mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00100000, iomemtype);
memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
"fpga", 0x00100000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}

18
hw/musicpal.c
View File

@ -386,7 +386,7 @@ static int mv88w8618_eth_init(SysBusDevice *dev)
dev->qdev.info->name, dev->qdev.id, s);
memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
MP_ETH_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
@ -593,7 +593,7 @@ static int musicpal_lcd_init(SysBusDevice *dev)
memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
"musicpal-lcd", MP_LCD_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
@ -713,7 +713,7 @@ static int mv88w8618_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_irq);
memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
"musicpal-pic", MP_PIC_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
@ -869,7 +869,7 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
"musicpal-pit", MP_PIT_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
@ -954,7 +954,7 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev)
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
"musicpal-flashcfg", MP_FLASHCFG_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
@ -1050,7 +1050,7 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
"musicpal-wlan", MP_WLAN_SIZE);
sysbus_init_mmio_region(dev, iomem);
sysbus_init_mmio(dev, iomem);
return 0;
}
@ -1256,7 +1256,7 @@ static int musicpal_gpio_init(SysBusDevice *dev)
memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
"musicpal-gpio", MP_GPIO_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
@ -1315,6 +1315,7 @@ static SysBusDeviceInfo musicpal_gpio_info = {
typedef struct musicpal_key_state {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t kbd_extended;
uint32_t pressed_keys;
qemu_irq out[8];
@ -1401,7 +1402,8 @@ static int musicpal_key_init(SysBusDevice *dev)
{
musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
sysbus_init_mmio(dev, 0x0, 0);
memory_region_init(&s->iomem, "dummy", 0);
sysbus_init_mmio(dev, &s->iomem);
s->kbd_extended = 0;
s->pressed_keys = 0;

4
hw/nseries.c
View File

@ -33,6 +33,7 @@
#include "loader.h"
#include "blockdev.h"
#include "sysbus.h"
#include "exec-memory.h"
/* Nokia N8x0 support */
struct n800_s {
@ -1275,11 +1276,12 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, struct arm_boot_info *binfo, int model)
{
MemoryRegion *sysmem = get_system_memory();
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
int sdram_size = binfo->ram_size;
DisplayState *ds;
s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
s->cpu = omap2420_mpu_init(sysmem, sdram_size, cpu_model);
/* Setup peripherals
*

45
hw/omap.h
View File

@ -76,6 +76,7 @@ struct omap_l4_agent_info_s {
int ta_region;
};
struct omap_target_agent_s {
MemoryRegion iomem;
struct omap_l4_s *bus;
int regions;
const struct omap_l4_region_s *start;
@ -84,7 +85,8 @@ struct omap_target_agent_s {
uint32_t control;
uint32_t status;
};
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
target_phys_addr_t base, int ta_num);
struct omap_target_agent_s;
struct omap_target_agent_s *omap_l4ta_get(
@ -92,16 +94,17 @@ struct omap_target_agent_s *omap_l4ta_get(
const struct omap_l4_region_s *regions,
const struct omap_l4_agent_info_s *agents,
int cs);
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
int iotype);
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr);
target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
int region);
int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write, void *opaque);
target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
int region);
/* OMAP2 SDRAM controller */
struct omap_sdrc_s;
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
target_phys_addr_t base);
void omap_sdrc_reset(struct omap_sdrc_s *s);
/* OMAP2 general purpose memory controller */
@ -431,9 +434,11 @@ enum omap_dma_model {
struct soc_dma_s;
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
void omap_dma_reset(struct soc_dma_s *s);
@ -658,7 +663,8 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr);
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr);
@ -725,8 +731,11 @@ void omap_tap_init(struct omap_target_agent_s *ta,
/* omap_lcdc.c */
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma, omap_clk clk);
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk);
/* omap_dss.c */
struct rfbi_chip_s {
@ -738,6 +747,7 @@ struct rfbi_chip_s {
struct omap_dss_s;
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
@ -747,6 +757,7 @@ void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
/* omap_mmc.c */
struct omap_mmc_s;
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk);
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
@ -758,8 +769,11 @@ void omap_mmc_enable(struct omap_mmc_s *s, int enable);
/* omap_i2c.c */
struct omap_i2c_s;
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
qemu_irq irq, qemu_irq *dma, omap_clk clk);
struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq,
qemu_irq *dma,
omap_clk clk);
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
void omap_i2c_reset(struct omap_i2c_s *s);
@ -822,8 +836,11 @@ struct omap_mpu_state_s {
MemoryRegion pwl_iomem;
MemoryRegion pwt_iomem;
MemoryRegion mpui_io_iomem;
MemoryRegion tap_iomem;
MemoryRegion imif_ram;
MemoryRegion emiff_ram;
MemoryRegion sdram;
MemoryRegion sram;
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
@ -952,7 +969,8 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
const char *core);
/* omap2.c */
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
const char *core);
# if TARGET_PHYS_ADDR_BITS == 32
@ -1125,7 +1143,4 @@ inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
# define cpu_register_io_memory debug_register_io_memory
# endif
/* Define when we want to reduce the number of IO regions registered. */
/*# define L4_MUX_HACK*/
#endif /* hw_omap_h */

8
hw/omap1.c
View File

@ -3849,7 +3849,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
omap1_dma_irq_map[i].intr);
}
s->dma = omap_dma_init(0xfffed800, dma_irqs,
s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory,
qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
@ -3884,7 +3884,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
omap_findclk(s, "clk32-kHz"));
s->lcd = omap_lcdc_init(0xfffec000,
s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
omap_dma_get_lcdch(s->dma),
omap_findclk(s, "lcd_ck"));
@ -3938,7 +3938,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
fprintf(stderr, "qemu: missing SecureDigital device\n");
exit(1);
}
s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
s->mmc = omap_mmc_init(0xfffb7800, system_memory, dinfo->bdrv,
qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
&s->drq[OMAP_DMA_MMC_TX],
omap_findclk(s, "mmc_ck"));
@ -3964,7 +3964,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck"));
omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck"));
s->i2c[0] = omap_i2c_init(0xfffb3800,
s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800,
qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));

207
hw/omap2.c
View File

@ -33,6 +33,7 @@
/* Enhanced Audio Controller (CODEC only) */
struct omap_eac_s {
qemu_irq irq;
MemoryRegion iomem;
uint16_t sysconfig;
uint8_t config[4];
@ -323,11 +324,16 @@ static void omap_eac_reset(struct omap_eac_s *s)
omap_eac_interrupt_update(s);
}
static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
uint32_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x000: /* CPCFR1 */
return s->config[0];
@ -435,10 +441,14 @@ static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
}
static void omap_eac_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x098: /* APD1LCR */
case 0x09c: /* APD1RCR */
@ -574,22 +584,15 @@ static void omap_eac_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_eac_readfn[] = {
omap_badwidth_read16,
omap_eac_read,
omap_badwidth_read16,
};
static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
omap_badwidth_write16,
omap_eac_write,
omap_badwidth_write16,
static const MemoryRegionOps omap_eac_ops = {
.read = omap_eac_read,
.write = omap_eac_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
int iomemtype;
struct omap_eac_s *s = (struct omap_eac_s *)
g_malloc0(sizeof(struct omap_eac_s));
@ -600,9 +603,9 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
AUD_register_card("OMAP EAC", &s->codec.card);
iomemtype = cpu_register_io_memory(omap_eac_readfn,
omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_eac_ops, s, "omap.eac",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
}
@ -610,6 +613,8 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
/* STI/XTI (emulation interface) console - reverse engineered only */
struct omap_sti_s {
qemu_irq irq;
MemoryRegion iomem;
MemoryRegion iomem_fifo;
CharDriverState *chr;
uint32_t sysconfig;
@ -639,10 +644,15 @@ static void omap_sti_reset(struct omap_sti_s *s)
omap_sti_interrupt_update(s);
}
static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* STI_REVISION */
return 0x10;
@ -676,10 +686,14 @@ static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
}
static void omap_sti_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* STI_REVISION */
case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
@ -721,31 +735,30 @@ static void omap_sti_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_sti_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_sti_read,
static const MemoryRegionOps omap_sti_ops = {
.read = omap_sti_read,
.write = omap_sti_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_sti_write,
};
static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
}
static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
int ch = addr >> 6;
uint8_t byte = value;
if (size != 1) {
return omap_badwidth_write8(opaque, addr, size);
}
if (ch == STI_TRACE_CONTROL_CHANNEL) {
/* Flush channel <i>value</i>. */
qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
@ -759,23 +772,17 @@ static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
omap_sti_fifo_read,
omap_badwidth_read8,
omap_badwidth_read8,
};
static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
omap_sti_fifo_write,
omap_badwidth_write8,
omap_badwidth_write8,
static const MemoryRegionOps omap_sti_fifo_ops = {
.read = omap_sti_fifo_read,
.write = omap_sti_fifo_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
int iomemtype;
struct omap_sti_s *s = (struct omap_sti_s *)
g_malloc0(sizeof(struct omap_sti_s));
@ -784,13 +791,13 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
s->chr = chr ?: qemu_chr_new("null", "null", NULL);
iomemtype = l4_register_io_memory(omap_sti_readfn,
omap_sti_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_sti_ops, s, "omap.sti",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
memory_region_init_io(&s->iomem_fifo, &omap_sti_fifo_ops, s,
"omap.sti.fifo", 0x10000);
memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
return s;
}
@ -993,6 +1000,8 @@ static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
struct omap_prcm_s {
qemu_irq irq[3];
struct omap_mpu_state_s *mpu;
MemoryRegion iomem0;
MemoryRegion iomem1;
uint32_t irqst[3];
uint32_t irqen[3];
@ -1031,11 +1040,16 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
}
static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_prcm_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
uint32_t ret;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x000: /* PRCM_REVISION */
return 0x10;
@ -1339,10 +1353,14 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
}
static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x000: /* PRCM_REVISION */
case 0x054: /* PRCM_VOLTST */
@ -1692,16 +1710,10 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_prcm_read,
};
static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_prcm_write,
static const MemoryRegionOps omap_prcm_ops = {
.read = omap_prcm_read,
.write = omap_prcm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_prcm_reset(struct omap_prcm_s *s)
@ -1788,7 +1800,6 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
struct omap_mpu_state_s *mpu)
{
int iomemtype;
struct omap_prcm_s *s = (struct omap_prcm_s *)
g_malloc0(sizeof(struct omap_prcm_s));
@ -1798,10 +1809,12 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
s->mpu = mpu;
omap_prcm_coldreset(s);
iomemtype = l4_register_io_memory(omap_prcm_readfn,
omap_prcm_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
omap_l4_attach(ta, 1, iomemtype);
memory_region_init_io(&s->iomem0, &omap_prcm_ops, s, "omap.pcrm0",
omap_l4_region_size(ta, 0));
memory_region_init_io(&s->iomem1, &omap_prcm_ops, s, "omap.pcrm1",
omap_l4_region_size(ta, 1));
omap_l4_attach(ta, 0, &s->iomem0);
omap_l4_attach(ta, 1, &s->iomem1);
return s;
}
@ -1809,6 +1822,7 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
/* System and Pinout control */
struct omap_sysctl_s {
struct omap_mpu_state_s *mpu;
MemoryRegion iomem;
uint32_t sysconfig;
uint32_t devconfig;
@ -2062,16 +2076,20 @@ static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
omap_sysctl_read8,
omap_badwidth_read32, /* TODO */
omap_sysctl_read,
};
static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
omap_sysctl_write8,
omap_badwidth_write32, /* TODO */
omap_sysctl_write,
static const MemoryRegionOps omap_sysctl_ops = {
.old_mmio = {
.read = {
omap_sysctl_read8,
omap_badwidth_read32, /* TODO */
omap_sysctl_read,
},
.write = {
omap_sysctl_write8,
omap_badwidth_write32, /* TODO */
omap_sysctl_write,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_sysctl_reset(struct omap_sysctl_s *s)
@ -2161,16 +2179,15 @@ static void omap_sysctl_reset(struct omap_sysctl_s *s)
static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
omap_clk iclk, struct omap_mpu_state_s *mpu)
{
int iomemtype;
struct omap_sysctl_s *s = (struct omap_sysctl_s *)
g_malloc0(sizeof(struct omap_sysctl_s));
s->mpu = mpu;
omap_sysctl_reset(s);
iomemtype = l4_register_io_memory(omap_sysctl_readfn,
omap_sysctl_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_sysctl_ops, s, "omap.sysctl",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
}
@ -2223,12 +2240,12 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
{ 0, OMAP_INT_24XX_SDMA_IRQ3 },
};
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
const char *core)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
g_malloc0(sizeof(struct omap_mpu_state_s));
ram_addr_t sram_base, q2_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[4];
DriveInfo *dinfo;
@ -2252,14 +2269,12 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_clk_init(s);
/* Memory-mapped stuff */
cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
(q2_base = qemu_ram_alloc(NULL, "omap2.dram",
s->sdram_size)) | IO_MEM_RAM);
cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
(sram_base = qemu_ram_alloc(NULL, "omap2.sram",
s->sram_size)) | IO_MEM_RAM);
memory_region_init_ram(&s->sdram, NULL, "omap2.dram", s->sdram_size);
memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size);
memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
cpu_irq = arm_pic_init_cpu(s->env);
@ -2284,18 +2299,18 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
omap2_dma_irq_map[i].intr);
}
s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
omap_findclk(s, "sdma_iclk"),
omap_findclk(s, "sdma_fclk"));
s->port->addr_valid = omap2_validate_addr;
/* Register SDRAM and SRAM ports for fast DMA transfers. */
soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(q2_base),
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
OMAP2_Q2_BASE, s->sdram_size);
soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(sram_base),
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
qdev_get_gpio_in(s->ih[0],
OMAP_INT_24XX_UART1_IRQ),
omap_findclk(s, "uart1_fclk"),
@ -2304,7 +2319,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
s->drq[OMAP24XX_DMA_UART1_RX],
"uart1",
serial_hds[0]);
s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
qdev_get_gpio_in(s->ih[0],
OMAP_INT_24XX_UART2_IRQ),
omap_findclk(s, "uart2_fclk"),
@ -2313,7 +2328,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
s->drq[OMAP24XX_DMA_UART2_RX],
"uart2",
serial_hds[0] ? serial_hds[1] : NULL);
s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
qdev_get_gpio_in(s->ih[0],
OMAP_INT_24XX_UART3_IRQ),
omap_findclk(s, "uart3_fclk"),
@ -2421,7 +2436,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
s->sdrc = omap_sdrc_init(0x68009000);
s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
s->gpmc = omap_gpmc_init(s, 0x6800a000,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
s->drq[OMAP24XX_DMA_GPMC]);
@ -2447,7 +2462,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_findclk(s, "spi2_fclk"),
omap_findclk(s, "spi2_iclk"));
s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
/* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
s->drq[OMAP24XX_DMA_DSS],
@ -2456,7 +2471,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_findclk(s, "dss_l3_iclk"),
omap_findclk(s, "dss_l4_iclk"));
omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
omap_findclk(s, "emul_ck"),
serial_hds[0] && serial_hds[1] && serial_hds[2] ?

71
hw/omap_dma.c
View File

@ -102,6 +102,7 @@ struct omap_dma_channel_s {
struct omap_dma_s {
struct soc_dma_s *dma;
MemoryRegion iomem;
struct omap_mpu_state_s *mpu;
omap_clk clk;
@ -1445,12 +1446,17 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
return 0;
}
static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int reg, ch;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
@ -1489,11 +1495,15 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
}
static void omap_dma_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int reg, ch;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
@ -1530,16 +1540,10 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
static CPUReadMemoryFunc * const omap_dma_readfn[] = {
omap_badwidth_read16,
omap_dma_read,
omap_badwidth_read16,
};
static CPUWriteMemoryFunc * const omap_dma_writefn[] = {
omap_badwidth_write16,
omap_dma_write,
omap_badwidth_write16,
static const MemoryRegionOps omap_dma_ops = {
.read = omap_dma_read,
.write = omap_dma_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_dma_request(void *opaque, int drq, int req)
@ -1615,10 +1619,11 @@ static void omap_dma_setcaps(struct omap_dma_s *s)
}
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
{
int iomemtype, num_irqs, memsize, i;
int num_irqs, memsize, i;
struct omap_dma_s *s = (struct omap_dma_s *)
g_malloc0(sizeof(struct omap_dma_s));
@ -1658,9 +1663,8 @@ struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, 1);
iomemtype = cpu_register_io_memory(omap_dma_readfn,
omap_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, memsize, iomemtype);
memory_region_init_io(&s->iomem, &omap_dma_ops, s, "omap.dma", memsize);
memory_region_add_subregion(sysmem, base, &s->iomem);
mpu->drq = s->dma->drq;
@ -1688,12 +1692,17 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
qemu_irq_raise(s->irq[3]);
}
static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int irqn = 0, chnum;
struct omap_dma_channel_s *ch;
if (size == 1) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x00: /* DMA4_REVISION */
return 0x40;
@ -1834,12 +1843,16 @@ static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
}
static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int chnum, irqn = 0;
struct omap_dma_channel_s *ch;
if (size == 1) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
@ -2021,23 +2034,18 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_dma4_readfn[] = {
omap_badwidth_read16,
omap_dma4_read,
omap_dma4_read,
};
static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
omap_badwidth_write16,
omap_dma4_write,
omap_dma4_write,
static const MemoryRegionOps omap_dma4_ops = {
.read = omap_dma4_read,
.write = omap_dma4_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)
{
int iomemtype, i;
int i;
struct omap_dma_s *s = (struct omap_dma_s *)
g_malloc0(sizeof(struct omap_dma_s));
@ -2065,9 +2073,8 @@ struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, !!s->dma->freq);
iomemtype = cpu_register_io_memory(omap_dma4_readfn,
omap_dma4_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &omap_dma4_ops, s, "omap.dma4", 0x1000);
memory_region_add_subregion(sysmem, base, &s->iomem);
mpu->drq = s->dma->drq;

169
hw/omap_dss.c
View File

@ -25,6 +25,7 @@ struct omap_dss_s {
qemu_irq irq;
qemu_irq drq;
DisplayState *state;
MemoryRegion iomem_diss1, iomem_disc1, iomem_rfbi1, iomem_venc1, iomem_im3;
int autoidle;
int control;
@ -167,10 +168,15 @@ void omap_dss_reset(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
return 0x20;
@ -201,10 +207,14 @@ static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
}
static void omap_diss_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
case 0x14: /* DSS_SYSSTATUS */
@ -230,22 +240,21 @@ static void omap_diss_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_diss1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_diss_read,
static const MemoryRegionOps omap_diss_ops = {
.read = omap_diss_read,
.write = omap_diss_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_diss1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_diss_write,
};
static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x000: /* DISPC_REVISION */
return 0x20;
@ -363,10 +372,14 @@ static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_disc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x010: /* DISPC_SYSCONFIG */
if (value & 2) /* SOFTRESET */
@ -570,16 +583,10 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_disc1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_disc_read,
};
static CPUWriteMemoryFunc * const omap_disc1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_disc_write,
static const MemoryRegionOps omap_disc_ops = {
.read = omap_disc_read,
.write = omap_disc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
@ -656,10 +663,15 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* RFBI_REVISION */
return 0x10;
@ -719,10 +731,14 @@ static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
}
static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x10: /* RFBI_SYSCONFIG */
if (value & 2) /* SOFTRESET */
@ -842,20 +858,19 @@ static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_rfbi1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_rfbi_read,
static const MemoryRegionOps omap_rfbi_ops = {
.read = omap_rfbi_read,
.write = omap_rfbi_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_rfbi_write,
};
static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* REV_ID */
case 0x04: /* STATUS */
@ -910,8 +925,12 @@ static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_venc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, size);
}
switch (addr) {
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
@ -961,20 +980,19 @@ static void omap_venc_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_venc1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_venc_read,
static const MemoryRegionOps omap_venc_ops = {
.read = omap_venc_read,
.write = omap_venc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_venc1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_venc_write,
};
static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x0a8: /* SBIMERRLOGA */
case 0x0b0: /* SBIMERRLOG */
@ -995,8 +1013,12 @@ static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
}
static void omap_im3_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
@ -1011,25 +1033,19 @@ static void omap_im3_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_im3_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_im3_read,
};
static CPUWriteMemoryFunc * const omap_im3_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_im3_write,
static const MemoryRegionOps omap_im3_ops = {
.read = omap_im3_read,
.write = omap_im3_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
{
int iomemtype[5];
struct omap_dss_s *s = (struct omap_dss_s *)
g_malloc0(sizeof(struct omap_dss_s));
@ -1037,21 +1053,22 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
s->drq = drq;
omap_dss_reset(s);
iomemtype[0] = l4_register_io_memory(omap_diss1_readfn,
omap_diss1_writefn, s);
iomemtype[1] = l4_register_io_memory(omap_disc1_readfn,
omap_disc1_writefn, s);
iomemtype[2] = l4_register_io_memory(omap_rfbi1_readfn,
omap_rfbi1_writefn, s);
iomemtype[3] = l4_register_io_memory(omap_venc1_readfn,
omap_venc1_writefn, s);
iomemtype[4] = cpu_register_io_memory(omap_im3_readfn,
omap_im3_writefn, s, DEVICE_NATIVE_ENDIAN);
omap_l4_attach(ta, 0, iomemtype[0]);
omap_l4_attach(ta, 1, iomemtype[1]);
omap_l4_attach(ta, 2, iomemtype[2]);
omap_l4_attach(ta, 3, iomemtype[3]);
cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]);
memory_region_init_io(&s->iomem_diss1, &omap_diss_ops, s, "omap.diss1",
omap_l4_region_size(ta, 0));
memory_region_init_io(&s->iomem_disc1, &omap_disc_ops, s, "omap.disc1",
omap_l4_region_size(ta, 1));
memory_region_init_io(&s->iomem_rfbi1, &omap_rfbi_ops, s, "omap.rfbi1",
omap_l4_region_size(ta, 2));
memory_region_init_io(&s->iomem_venc1, &omap_venc_ops, s, "omap.venc1",
omap_l4_region_size(ta, 3));
memory_region_init_io(&s->iomem_im3, &omap_im3_ops, s,
"omap.im3", 0x1000);
omap_l4_attach(ta, 0, &s->iomem_diss1);
omap_l4_attach(ta, 1, &s->iomem_disc1);
omap_l4_attach(ta, 2, &s->iomem_rfbi1);
omap_l4_attach(ta, 3, &s->iomem_venc1);
memory_region_add_subregion(sysmem, l3_base, &s->iomem_im3);
#if 0
s->state = graphic_console_init(omap_update_display,

95
hw/omap_gpio.c
View File

@ -37,6 +37,7 @@ struct omap_gpio_s {
struct omap_gpif_s {
SysBusDevice busdev;
MemoryRegion iomem;
int mpu_model;
void *clk;
struct omap_gpio_s omap1;
@ -60,11 +61,16 @@ static void omap_gpio_set(void *opaque, int line, int level)
}
}
static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_gpio_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (offset) {
case 0x00: /* DATA_INPUT */
return s->inputs & s->pins;
@ -94,13 +100,17 @@ static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
}
static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (offset) {
case 0x00: /* DATA_INPUT */
OMAP_RO_REG(addr);
@ -156,16 +166,10 @@ static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
}
/* *Some* sources say the memory region is 32-bit. */
static CPUReadMemoryFunc * const omap_gpio_readfn[] = {
omap_badwidth_read16,
omap_gpio_read,
omap_badwidth_read16,
};
static CPUWriteMemoryFunc * const omap_gpio_writefn[] = {
omap_badwidth_write16,
omap_gpio_write,
omap_badwidth_write16,
static const MemoryRegionOps omap_gpio_ops = {
.read = omap_gpio_read,
.write = omap_gpio_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_gpio_reset(struct omap_gpio_s *s)
@ -183,6 +187,7 @@ struct omap2_gpio_s {
qemu_irq irq[2];
qemu_irq wkup;
qemu_irq *handler;
MemoryRegion iomem;
uint8_t revision;
uint8_t config[2];
@ -200,6 +205,7 @@ struct omap2_gpio_s {
struct omap2_gpif_s {
SysBusDevice busdev;
MemoryRegion iomem;
int mpu_model;
void *iclk;
void *fclk[6];
@ -563,16 +569,20 @@ static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap2_gpio_module_readfn[] = {
omap2_gpio_module_readp,
omap2_gpio_module_readp,
omap2_gpio_module_read,
};
static CPUWriteMemoryFunc * const omap2_gpio_module_writefn[] = {
omap2_gpio_module_writep,
omap2_gpio_module_writep,
omap2_gpio_module_write,
static const MemoryRegionOps omap2_gpio_module_ops = {
.old_mmio = {
.read = {
omap2_gpio_module_readp,
omap2_gpio_module_readp,
omap2_gpio_module_read,
},
.write = {
omap2_gpio_module_writep,
omap2_gpio_module_writep,
omap2_gpio_module_write,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_gpif_reset(DeviceState *dev)
@ -594,7 +604,8 @@ static void omap2_gpif_reset(DeviceState *dev)
s->gpo = 0;
}
static uint32_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
@ -623,7 +634,7 @@ static uint32_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr)
}
static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
@ -651,16 +662,10 @@ static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap2_gpif_top_readfn[] = {
omap2_gpif_top_read,
omap2_gpif_top_read,
omap2_gpif_top_read,
};
static CPUWriteMemoryFunc * const omap2_gpif_top_writefn[] = {
omap2_gpif_top_write,
omap2_gpif_top_write,
omap2_gpif_top_write,
static const MemoryRegionOps omap2_gpif_top_ops = {
.read = omap2_gpif_top_read,
.write = omap2_gpif_top_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int omap_gpio_init(SysBusDevice *dev)
@ -672,11 +677,9 @@ static int omap_gpio_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, omap_gpio_set, 16);
qdev_init_gpio_out(&dev->qdev, s->omap1.handler, 16);
sysbus_init_irq(dev, &s->omap1.irq);
sysbus_init_mmio(dev, 0x1000,
cpu_register_io_memory(omap_gpio_readfn,
omap_gpio_writefn,
&s->omap1,
DEVICE_NATIVE_ENDIAN));
memory_region_init_io(&s->iomem, &omap_gpio_ops, &s->omap1,
"omap.gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
@ -689,10 +692,9 @@ static int omap2_gpio_init(SysBusDevice *dev)
}
if (s->mpu_model < omap3430) {
s->modulecount = (s->mpu_model < omap2430) ? 4 : 5;
sysbus_init_mmio(dev, 0x1000,
cpu_register_io_memory(omap2_gpif_top_readfn,
omap2_gpif_top_writefn, s,
DEVICE_NATIVE_ENDIAN));
memory_region_init_io(&s->iomem, &omap2_gpif_top_ops, s,
"omap2.gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
} else {
s->modulecount = 6;
}
@ -710,10 +712,9 @@ static int omap2_gpio_init(SysBusDevice *dev)
sysbus_init_irq(dev, &m->irq[0]); /* mpu irq */
sysbus_init_irq(dev, &m->irq[1]); /* dsp irq */
sysbus_init_irq(dev, &m->wkup);
sysbus_init_mmio(dev, 0x1000,
cpu_register_io_memory(omap2_gpio_module_readfn,
omap2_gpio_module_writefn,
m, DEVICE_NATIVE_ENDIAN));
memory_region_init_io(&m->iomem, &omap2_gpio_module_ops, m,
"omap.gpio-module", 0x1000);
sysbus_init_mmio(dev, &m->iomem);
}
return 0;
}

32
hw/omap_gptimer.c
View File

@ -23,6 +23,7 @@
/* GP timers */
struct omap_gp_timer_s {
MemoryRegion iomem;
qemu_irq irq;
qemu_irq wkup;
qemu_irq in;
@ -337,12 +338,6 @@ static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
}
}
static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = {
omap_badwidth_read32,
omap_gp_timer_readh,
omap_gp_timer_readw,
};
static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
@ -454,16 +449,25 @@ static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
s->writeh = (uint16_t) value;
}
static CPUWriteMemoryFunc * const omap_gp_timer_writefn[] = {
omap_badwidth_write32,
omap_gp_timer_writeh,
omap_gp_timer_write,
static const MemoryRegionOps omap_gp_timer_ops = {
.old_mmio = {
.read = {
omap_badwidth_read32,
omap_gp_timer_readh,
omap_gp_timer_readw,
},
.write = {
omap_badwidth_write32,
omap_gp_timer_writeh,
omap_gp_timer_write,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk)
{
int iomemtype;
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
g_malloc0(sizeof(struct omap_gp_timer_s));
@ -476,9 +480,9 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
omap_gp_timer_reset(s);
omap_gp_timer_clk_setup(s);
iomemtype = l4_register_io_memory(omap_gp_timer_readfn,
omap_gp_timer_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_gp_timer_ops, s, "omap.gptimer",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
}

45
hw/omap_i2c.c
View File

@ -21,6 +21,7 @@
#include "omap.h"
struct omap_i2c_s {
MemoryRegion iomem;
qemu_irq irq;
qemu_irq drq[2];
i2c_bus *bus;
@ -409,22 +410,28 @@ static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_i2c_readfn[] = {
omap_badwidth_read16,
omap_i2c_read,
omap_badwidth_read16,
static const MemoryRegionOps omap_i2c_ops = {
.old_mmio = {
.read = {
omap_badwidth_read16,
omap_i2c_read,
omap_badwidth_read16,
},
.write = {
omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
omap_i2c_write,
omap_badwidth_write16,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_i2c_writefn[] = {
omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
omap_i2c_write,
omap_badwidth_write16,
};
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
qemu_irq irq, qemu_irq *dma, omap_clk clk)
struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq,
qemu_irq *dma,
omap_clk clk)
{
int iomemtype;
struct omap_i2c_s *s = (struct omap_i2c_s *)
g_malloc0(sizeof(struct omap_i2c_s));
@ -436,9 +443,8 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
iomemtype = cpu_register_io_memory(omap_i2c_readfn,
omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", 0x800);
memory_region_add_subregion(sysmem, base, &s->iomem);
return s;
}
@ -446,7 +452,6 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
{
int iomemtype;
struct omap_i2c_s *s = (struct omap_i2c_s *)
g_malloc0(sizeof(struct omap_i2c_s));
@ -457,9 +462,9 @@ struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
iomemtype = l4_register_io_memory(omap_i2c_readfn,
omap_i2c_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap2.i2c",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
}

4
hw/omap_intc.c
View File

@ -369,7 +369,7 @@ static int omap_intc_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s,
"omap-intc", s->size);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
return 0;
}
@ -600,7 +600,7 @@ static int omap2_intc_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s,
"omap2-intc", 0x1000);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
return 0;
}

182
hw/omap_l4.c
View File

@ -20,129 +20,23 @@
#include "hw.h"
#include "omap.h"
#ifdef L4_MUX_HACK
static int omap_l4_io_entries;
static int omap_cpu_io_entry;
static struct omap_l4_entry {
CPUReadMemoryFunc * const *mem_read;
CPUWriteMemoryFunc * const *mem_write;
void *opaque;
} *omap_l4_io_entry;
static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
static void **omap_l4_io_opaque;
int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write, void *opaque)
{
omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
return omap_l4_io_entries ++;
}
static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
}
static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
}
static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
}
static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
}
static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
}
static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
}
static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
omap_l4_io_readb,
omap_l4_io_readh,
omap_l4_io_readw,
};
static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
omap_l4_io_writeb,
omap_l4_io_writeh,
omap_l4_io_writew,
};
#else
int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
void *opaque)
{
return cpu_register_io_memory(mem_read, mem_write, opaque,
DEVICE_NATIVE_ENDIAN);
}
#endif
struct omap_l4_s {
MemoryRegion *address_space;
target_phys_addr_t base;
int ta_num;
struct omap_target_agent_s ta[0];
};
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
target_phys_addr_t base, int ta_num)
{
struct omap_l4_s *bus = g_malloc0(
sizeof(*bus) + ta_num * sizeof(*bus->ta));
bus->address_space = address_space;
bus->ta_num = ta_num;
bus->base = base;
#ifdef L4_MUX_HACK
omap_l4_io_entries = 1;
omap_l4_io_entry = g_malloc0(125 * sizeof(*omap_l4_io_entry));
omap_cpu_io_entry =
cpu_register_io_memory(omap_l4_io_readfn,
omap_l4_io_writefn, bus, DEVICE_NATIVE_ENDIAN);
# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
omap_l4_io_readb_fn = g_malloc0(sizeof(void *) * L4_PAGES);
omap_l4_io_readh_fn = g_malloc0(sizeof(void *) * L4_PAGES);
omap_l4_io_readw_fn = g_malloc0(sizeof(void *) * L4_PAGES);
omap_l4_io_writeb_fn = g_malloc0(sizeof(void *) * L4_PAGES);
omap_l4_io_writeh_fn = g_malloc0(sizeof(void *) * L4_PAGES);
omap_l4_io_writew_fn = g_malloc0(sizeof(void *) * L4_PAGES);
omap_l4_io_opaque = g_malloc0(sizeof(void *) * L4_PAGES);
#endif
return bus;
}
@ -152,10 +46,21 @@ target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
return ta->bus->base + ta->start[region].offset;
}
static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
int region)
{
return ta->start[region].size;
}
static uint64_t omap_l4ta_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x00: /* COMPONENT */
return s->component;
@ -172,10 +77,14 @@ static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
}
static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* COMPONENT */
case 0x28: /* AGENT_STATUS */
@ -193,16 +102,10 @@ static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
omap_badwidth_read16,
omap_l4ta_read,
omap_badwidth_read16,
};
static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_l4ta_write,
static const MemoryRegionOps omap_l4ta_ops = {
.read = omap_l4ta_read,
.write = omap_l4ta_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
@ -210,7 +113,7 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
const struct omap_l4_agent_info_s *agents,
int cs)
{
int i, iomemtype;
int i;
struct omap_target_agent_s *ta = NULL;
const struct omap_l4_agent_info_s *info = NULL;
@ -233,21 +136,17 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
ta->status = 0x00000000;
ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
iomemtype = l4_register_io_memory(omap_l4ta_readfn,
omap_l4ta_writefn, ta);
ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
memory_region_init_io(&ta->iomem, &omap_l4ta_ops, ta, "omap.l4ta",
omap_l4_region_size(ta, info->ta_region));
omap_l4_attach(ta, info->ta_region, &ta->iomem);
return ta;
}
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
int iotype)
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr)
{
target_phys_addr_t base;
ssize_t size;
#ifdef L4_MUX_HACK
int i;
#endif
if (region < 0 || region >= ta->regions) {
fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
@ -255,23 +154,8 @@ target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
}
base = ta->bus->base + ta->start[region].offset;
size = ta->start[region].size;
if (iotype) {
#ifndef L4_MUX_HACK
cpu_register_physical_memory(base, size, iotype);
#else
cpu_register_physical_memory(base, size, omap_cpu_io_entry);
i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
}
#endif
if (mr) {
memory_region_add_subregion(ta->bus->address_space, base, mr);
}
return base;

33
hw/omap_lcdc.c
View File

@ -22,6 +22,7 @@
#include "framebuffer.h"
struct omap_lcd_panel_s {
MemoryRegion iomem;
qemu_irq irq;
DisplayState *state;
@ -323,7 +324,8 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
}
}
static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_lcdc_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@ -356,7 +358,7 @@ static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@ -399,16 +401,10 @@ static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_lcdc_readfn[] = {
omap_lcdc_read,
omap_lcdc_read,
omap_lcdc_read,
};
static CPUWriteMemoryFunc * const omap_lcdc_writefn[] = {
omap_lcdc_write,
omap_lcdc_write,
omap_lcdc_write,
static const MemoryRegionOps omap_lcdc_ops = {
.read = omap_lcdc_read,
.write = omap_lcdc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
void omap_lcdc_reset(struct omap_lcd_panel_s *s)
@ -433,10 +429,12 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
s->ctrl = 0;
}
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma, omap_clk clk)
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk)
{
int iomemtype;
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
g_malloc0(sizeof(struct omap_lcd_panel_s));
@ -444,9 +442,8 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
s->dma = dma;
omap_lcdc_reset(s);
iomemtype = cpu_register_io_memory(omap_lcdc_readfn,
omap_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem);
s->state = graphic_console_init(omap_update_display,
omap_invalidate_display,

44
hw/omap_mmc.c
View File

@ -24,6 +24,7 @@ struct omap_mmc_s {
qemu_irq irq;
qemu_irq *dma;
qemu_irq coverswitch;
MemoryRegion iomem;
omap_clk clk;
SDState *card;
uint16_t last_cmd;
@ -305,11 +306,15 @@ void omap_mmc_reset(struct omap_mmc_s *host)
host->clkdiv = 0;
}
static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
static uint64_t omap_mmc_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
uint16_t i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
offset &= OMAP_MPUI_REG_MASK;
if (size != 2) {
return omap_badwidth_read16(opaque, offset);
}
switch (offset) {
case 0x00: /* MMC_CMD */
@ -395,11 +400,14 @@ static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
}
static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
int i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
offset &= OMAP_MPUI_REG_MASK;
if (size != 2) {
return omap_badwidth_write16(opaque, offset, value);
}
switch (offset) {
case 0x00: /* MMC_CMD */
@ -540,16 +548,10 @@ static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
}
}
static CPUReadMemoryFunc * const omap_mmc_readfn[] = {
omap_badwidth_read16,
omap_mmc_read,
omap_badwidth_read16,
};
static CPUWriteMemoryFunc * const omap_mmc_writefn[] = {
omap_badwidth_write16,
omap_mmc_write,
omap_badwidth_write16,
static const MemoryRegionOps omap_mmc_ops = {
.read = omap_mmc_read,
.write = omap_mmc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mmc_cover_cb(void *opaque, int line, int level)
@ -571,10 +573,10 @@ static void omap_mmc_cover_cb(void *opaque, int line, int level)
}
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
{
int iomemtype;
struct omap_mmc_s *s = (struct omap_mmc_s *)
g_malloc0(sizeof(struct omap_mmc_s));
@ -586,9 +588,8 @@ struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
omap_mmc_reset(s);
iomemtype = cpu_register_io_memory(omap_mmc_readfn,
omap_mmc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
memory_region_init_io(&s->iomem, &omap_mmc_ops, s, "omap.mmc", 0x800);
memory_region_add_subregion(sysmem, base, &s->iomem);
/* Instantiate the storage */
s->card = sd_init(bd, 0);
@ -600,7 +601,6 @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
omap_clk fclk, omap_clk iclk)
{
int iomemtype;
struct omap_mmc_s *s = (struct omap_mmc_s *)
g_malloc0(sizeof(struct omap_mmc_s));
@ -612,9 +612,9 @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
omap_mmc_reset(s);
iomemtype = l4_register_io_memory(omap_mmc_readfn,
omap_mmc_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_mmc_ops, s, "omap.mmc",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
/* Instantiate the storage */
s->card = sd_init(bd, 0);

39
hw/omap_sdrc.c
View File

@ -22,6 +22,7 @@
/* SDRAM Controller Subsystem */
struct omap_sdrc_s {
MemoryRegion iomem;
uint8_t config;
};
@ -30,10 +31,15 @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
s->config = 0x10;
}
static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_sdrc_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* SDRC_REVISION */
return 0x20;
@ -81,10 +87,14 @@ static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* SDRC_REVISION */
case 0x14: /* SDRC_SYSSTATUS */
@ -97,7 +107,7 @@ static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
case 0x10: /* SDRC_SYSCONFIG */
if ((value >> 3) != 0x2)
fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
__FUNCTION__, value >> 3);
__FUNCTION__, (unsigned)value >> 3);
if (value & 2)
omap_sdrc_reset(s);
s->config = value & 0x18;
@ -137,29 +147,22 @@ static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_sdrc_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_sdrc_read,
static const MemoryRegionOps omap_sdrc_ops = {
.read = omap_sdrc_read,
.write = omap_sdrc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_sdrc_write,
};
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
target_phys_addr_t base)
{
int iomemtype;
struct omap_sdrc_s *s = (struct omap_sdrc_s *)
g_malloc0(sizeof(struct omap_sdrc_s));
omap_sdrc_reset(s);
iomemtype = cpu_register_io_memory(omap_sdrc_readfn,
omap_sdrc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &omap_sdrc_ops, s, "omap.sdrc", 0x1000);
memory_region_add_subregion(sysmem, base, &s->iomem);
return s;
}

37
hw/omap_spi.c
View File

@ -24,6 +24,7 @@
/* Multichannel SPI */
struct omap_mcspi_s {
MemoryRegion iomem;
qemu_irq irq;
int chnum;
@ -129,12 +130,17 @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
omap_mcspi_interrupt_update(s);
}
static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
uint32_t ret;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* MCSPI_REVISION */
return 0x91;
@ -199,11 +205,15 @@ static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* MCSPI_REVISION */
case 0x14: /* MCSPI_SYSSTATUS */
@ -267,7 +277,7 @@ static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
if (((value >> 12) & 3) == 3) /* TRM */
fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
if (((value >> 7) & 0x1f) < 3) /* WL */
fprintf(stderr, "%s: invalid WL value (%i)\n",
fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
__FUNCTION__, (value >> 7) & 0x1f);
s->ch[ch].config = value & 0x7fffff;
break;
@ -298,22 +308,15 @@ static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_mcspi_read,
};
static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_mcspi_write,
static const MemoryRegionOps omap_mcspi_ops = {
.read = omap_mcspi_read,
.write = omap_mcspi_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
int iomemtype;
struct omap_mcspi_s *s = (struct omap_mcspi_s *)
g_malloc0(sizeof(struct omap_mcspi_s));
struct omap_mcspi_ch_s *ch = s->ch;
@ -327,9 +330,9 @@ struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
}
omap_mcspi_reset(s);
iomemtype = l4_register_io_memory(omap_mcspi_readfn,
omap_mcspi_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_mcspi_ops, s, "omap.mcspi",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
}

97
hw/omap_sx1.c
View File

@ -59,46 +59,28 @@
* - 1 RTC
*/
static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
static uint64_t static_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
uint32_t *val = (uint32_t *) opaque;
uint32_t mask = (4 / size) - 1;
return *val >> ((offset & 3) << 3);
}
static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
return *val >> ((offset & mask) << 3);
}
static void static_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
#ifdef SPY
printf("%s: value %08lx written at " PA_FMT "\n",
__FUNCTION__, value, offset);
printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n",
__func__, value, size, (int)offset);
#endif
}
static CPUReadMemoryFunc * const static_readfn[] = {
static_readb,
static_readh,
static_readw,
};
static CPUWriteMemoryFunc * const static_writefn[] = {
static_write,
static_write,
static_write,
static const MemoryRegionOps static_ops = {
.read = static_read,
.write = static_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define sdram_size 0x02000000
@ -123,7 +105,9 @@ static void sx1_init(ram_addr_t ram_size,
{
struct omap_mpu_state_s *cpu;
MemoryRegion *address_space = get_system_memory();
int io;
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
static uint32_t cs0val = 0x00213090;
static uint32_t cs1val = 0x00215070;
static uint32_t cs2val = 0x00001139;
@ -140,20 +124,25 @@ static void sx1_init(ram_addr_t ram_size,
cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
qemu_ram_alloc(NULL, "omap_sx1.flash0-0",
flash_size) | IO_MEM_ROM);
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
memory_region_init_io(&cs[0], &static_ops, &cs0val,
"sx1.cs0", OMAP_CS0_SIZE - flash_size);
memory_region_add_subregion(address_space,
OMAP_CS0_BASE + flash_size, &cs[0]);
memory_region_init_io(&cs[2], &static_ops, &cs2val,
"sx1.cs2", OMAP_CS2_SIZE);
memory_region_add_subregion(address_space,
OMAP_CS2_BASE, &cs[2]);
memory_region_init_io(&cs[3], &static_ops, &cs3val,
"sx1.cs3", OMAP_CS3_SIZE);
memory_region_add_subregion(address_space,
OMAP_CS2_BASE, &cs[3]);
fl_idx = 0;
#ifdef TARGET_WORDS_BIGENDIAN
@ -176,13 +165,14 @@ static void sx1_init(ram_addr_t ram_size,
if ((version == 1) &&
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,
qemu_ram_alloc(NULL, "omap_sx1.flash1-0",
flash1_size) | IO_MEM_ROM);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io);
memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size);
memory_region_set_readonly(flash_1, true);
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
memory_region_init_io(&cs[1], &static_ops, &cs1val,
"sx1.cs1", OMAP_CS1_SIZE - flash1_size);
memory_region_add_subregion(address_space,
OMAP_CS1_BASE + flash1_size, &cs[1]);
if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL,
"omap_sx1.flash1-1", flash1_size,
@ -194,9 +184,10 @@ static void sx1_init(ram_addr_t ram_size,
}
fl_idx++;
} else {
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
memory_region_init_io(&cs[1], &static_ops, &cs1val,
"sx1.cs1", OMAP_CS1_SIZE);
memory_region_add_subregion(address_space,
OMAP_CS1_BASE, &cs[1]);
}
if (!kernel_filename && !fl_idx) {

30
hw/omap_synctimer.c
View File

@ -21,6 +21,7 @@
#include "qemu-timer.h"
#include "omap.h"
struct omap_synctimer_s {
MemoryRegion iomem;
uint32_t val;
uint16_t readh;
};
@ -65,22 +66,26 @@ static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
}
}
static CPUReadMemoryFunc * const omap_synctimer_readfn[] = {
omap_badwidth_read32,
omap_synctimer_readh,
omap_synctimer_readw,
};
static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
}
static CPUWriteMemoryFunc * const omap_synctimer_writefn[] = {
omap_badwidth_write32,
omap_synctimer_write,
omap_synctimer_write,
static const MemoryRegionOps omap_synctimer_ops = {
.old_mmio = {
.read = {
omap_badwidth_read32,
omap_synctimer_readh,
omap_synctimer_readw,
},
.write = {
omap_badwidth_write32,
omap_synctimer_write,
omap_synctimer_write,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
@ -89,8 +94,9 @@ struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
struct omap_synctimer_s *s = g_malloc0(sizeof(*s));
omap_synctimer_reset(s);
omap_l4_attach(ta, 0, l4_register_io_memory(
omap_synctimer_readfn, omap_synctimer_writefn, s));
memory_region_init_io(&s->iomem, &omap_synctimer_ops, s, "omap.synctimer",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
}

32
hw/omap_tap.c
View File

@ -22,10 +22,15 @@
#include "omap.h"
/* TEST-Chip-level TAP */
static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_tap_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x204: /* IDCODE_reg */
switch (s->mpu_model) {
@ -87,26 +92,25 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
}
static void omap_tap_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
OMAP_BAD_REG(addr);
}
static CPUReadMemoryFunc * const omap_tap_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_tap_read,
};
static CPUWriteMemoryFunc * const omap_tap_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_tap_write,
static const MemoryRegionOps omap_tap_ops = {
.read = omap_tap_read,
.write = omap_tap_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_mpu_state_s *mpu)
{
omap_l4_attach(ta, 0, l4_register_io_memory(
omap_tap_readfn, omap_tap_writefn, mpu));
memory_region_init_io(&mpu->tap_iomem, &omap_tap_ops, mpu, "omap.tap",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &mpu->tap_iomem);
}

41
hw/omap_uart.c
View File

@ -26,6 +26,7 @@
/* UARTs */
struct omap_uart_s {
MemoryRegion iomem;
target_phys_addr_t base;
SerialState *serial; /* TODO */
struct omap_target_agent_s *ta;
@ -68,11 +69,15 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
return s;
}
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
addr &= 0xff;
if (size == 4) {
return omap_badwidth_read8(opaque, addr);
}
switch (addr) {
case 0x20: /* MDR1 */
return s->mdr[0];
@ -103,11 +108,14 @@ static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
}
static void omap_uart_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
addr &= 0xff;
if (size == 4) {
return omap_badwidth_write8(opaque, addr, value);
}
switch (addr) {
case 0x20: /* MDR1 */
s->mdr[0] = value & 0x7f;
@ -145,32 +153,27 @@ static void omap_uart_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_uart_readfn[] = {
omap_uart_read,
omap_uart_read,
omap_badwidth_read8,
static const MemoryRegionOps omap_uart_ops = {
.read = omap_uart_read,
.write = omap_uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
omap_uart_write,
omap_uart_write,
omap_badwidth_write8,
};
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
{
target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
target_phys_addr_t base = omap_l4_attach(ta, 0, NULL);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr);
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN);
memory_region_init_io(&s->iomem, &omap_uart_ops, s, "omap.uart", 0x100);
s->ta = ta;
cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
return s;
}

2
hw/onenand.c
View File

@ -791,7 +791,7 @@ static int onenand_initfn(SysBusDevice *dev)
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
onenand_mem_setup(s);
sysbus_init_irq(dev, &s->intr);
sysbus_init_mmio_region(dev, &s->container);
sysbus_init_mmio(dev, &s->container);
vmstate_register(&dev->qdev,
((s->shift & 0x7f) << 24)
| ((s->id.man & 0xff) << 16)

4
hw/opencores_eth.c
View File

@ -708,11 +708,11 @@ static int sysbus_open_eth_init(SysBusDevice *dev)
memory_region_init_io(&s->reg_io, &open_eth_reg_ops, s,
"open_eth.regs", 0x54);
sysbus_init_mmio_region(dev, &s->reg_io);
sysbus_init_mmio(dev, &s->reg_io);
memory_region_init_io(&s->desc_io, &open_eth_desc_ops, s,
"open_eth.desc", 0x400);
sysbus_init_mmio_region(dev, &s->desc_io);
sysbus_init_mmio(dev, &s->desc_io);
sysbus_init_irq(dev, &s->irq);

27
hw/parallel.c
View File

@ -65,6 +65,7 @@
#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
typedef struct ParallelState {
MemoryRegion iomem;
uint8_t dataw;
uint8_t datar;
uint8_t status;
@ -555,24 +556,20 @@ static void parallel_mm_writel (void *opaque,
parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}
static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
&parallel_mm_readb,
&parallel_mm_readw,
&parallel_mm_readl,
};
static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
&parallel_mm_writeb,
&parallel_mm_writew,
&parallel_mm_writel,
static const MemoryRegionOps parallel_mm_ops = {
.old_mmio = {
.read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
.write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
/* If fd is zero, it means that the parallel device uses the console */
bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
bool parallel_mm_init(MemoryRegion *address_space,
target_phys_addr_t base, int it_shift, qemu_irq irq,
CharDriverState *chr)
{
ParallelState *s;
int io_sw;
s = g_malloc0(sizeof(ParallelState));
s->irq = irq;
@ -580,9 +577,9 @@ bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
s->it_shift = it_shift;
qemu_register_reset(parallel_reset, s);
io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw,
s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
memory_region_init_io(&s->iomem, &parallel_mm_ops, s,
"parallel", 8 << it_shift);
memory_region_add_subregion(address_space, base, &s->iomem);
return true;
}

3
hw/pc.h
View File

@ -55,7 +55,8 @@ static inline bool parallel_init(int index, CharDriverState *chr)
return true;
}
bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
bool parallel_mm_init(MemoryRegion *address_space,
target_phys_addr_t base, int it_shift, qemu_irq irq,
CharDriverState *chr);
/* i8259.c */

1
hw/pci_host.h
View File

@ -34,6 +34,7 @@ struct PCIHostState {
SysBusDevice busdev;
MemoryRegion conf_mem;
MemoryRegion data_mem;
MemoryRegion mmcfg;
MemoryRegion *address_space;
uint32_t config_reg;
PCIBus *bus;

27
hw/pl011.c
View File

@ -12,6 +12,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t readbuff;
uint32_t flags;
uint32_t lcr;
@ -53,7 +54,8 @@ static void pl011_update(pl011_state *s)
qemu_set_irq(s->irq, flags != 0);
}
static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl011_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
uint32_t c;
@ -123,7 +125,7 @@ static void pl011_set_read_trigger(pl011_state *s)
}
static void pl011_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
unsigned char ch;
@ -223,16 +225,10 @@ static void pl011_event(void *opaque, int event)
pl011_put_fifo(opaque, 0x400);
}
static CPUReadMemoryFunc * const pl011_readfn[] = {
pl011_read,
pl011_read,
pl011_read
};
static CPUWriteMemoryFunc * const pl011_writefn[] = {
pl011_write,
pl011_write,
pl011_write
static const MemoryRegionOps pl011_ops = {
.read = pl011_read,
.write = pl011_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_pl011 = {
@ -262,13 +258,10 @@ static const VMStateDescription vmstate_pl011 = {
static int pl011_init(SysBusDevice *dev, const unsigned char *id)
{
int iomemtype;
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
iomemtype = cpu_register_io_memory(pl011_readfn,
pl011_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000,iomemtype);
memory_region_init_io(&s->iomem, &pl011_ops, s, "pl011", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->id = id;
s->chr = qdev_init_chardev(&dev->qdev);

29
hw/pl022.c
View File

@ -42,6 +42,7 @@ do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t cr0;
uint32_t cr1;
uint32_t bitmask;
@ -130,7 +131,8 @@ static void pl022_xfer(pl022_state *s)
pl022_update(s);
}
static uint32_t pl022_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl022_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
int val;
@ -173,7 +175,7 @@ static uint32_t pl022_read(void *opaque, target_phys_addr_t offset)
}
static void pl022_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
@ -193,7 +195,7 @@ static void pl022_write(void *opaque, target_phys_addr_t offset,
break;
case 0x08: /* DR */
if (s->tx_fifo_len < 8) {
DPRINTF("TX %02x\n", value);
DPRINTF("TX %02x\n", (unsigned)value);
s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
s->tx_fifo_len++;
@ -227,16 +229,10 @@ static void pl022_reset(pl022_state *s)
s->sr = PL022_SR_TFE | PL022_SR_TNF;
}
static CPUReadMemoryFunc * const pl022_readfn[] = {
pl022_read,
pl022_read,
pl022_read
};
static CPUWriteMemoryFunc * const pl022_writefn[] = {
pl022_write,
pl022_write,
pl022_write
static const MemoryRegionOps pl022_ops = {
.read = pl022_read,
.write = pl022_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_pl022 = {
@ -279,12 +275,9 @@ static const VMStateDescription vmstate_pl022 = {
static int pl022_init(SysBusDevice *dev)
{
pl022_state *s = FROM_SYSBUS(pl022_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(pl022_readfn,
pl022_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl022_ops, s, "pl022", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->ssi = ssi_create_bus(&dev->qdev, "ssi");
pl022_reset(s);

30
hw/pl031.c
View File

@ -32,6 +32,7 @@ do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
QEMUTimer *timer;
qemu_irq irq;
@ -105,7 +106,8 @@ static void pl031_set_alarm(pl031_state *s)
}
}
static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
@ -141,7 +143,7 @@ static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
}
static void pl031_write(void * opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
@ -186,31 +188,19 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
}
}
static CPUWriteMemoryFunc * const pl031_writefn[] = {
pl031_write,
pl031_write,
pl031_write
};
static CPUReadMemoryFunc * const pl031_readfn[] = {
pl031_read,
pl031_read,
pl031_read
static const MemoryRegionOps pl031_ops = {
.read = pl031_read,
.write = pl031_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl031_init(SysBusDevice *dev)
{
int iomemtype;
pl031_state *s = FROM_SYSBUS(pl031_state, dev);
struct tm tm;
iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s,
DEVICE_NATIVE_ENDIAN);
if (iomemtype == -1) {
hw_error("pl031_init: Can't register I/O memory\n");
}
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
/* ??? We assume vm_clock is zero at this point. */

2
hw/pl041.c
View File

@ -543,7 +543,7 @@ static int pl041_init(SysBusDevice *dev)
/* Connect the device to the sysbus */
memory_region_init_io(&s->iomem, &pl041_ops, s, "pl041", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
/* Init the codec */

27
hw/pl050.c
View File

@ -12,6 +12,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
void *dev;
uint32_t cr;
uint32_t clk;
@ -57,7 +58,8 @@ static void pl050_update(void *opaque, int level)
qemu_set_irq(s->irq, raise);
}
static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl050_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
if (offset >= 0xfe0 && offset < 0x1000)
@ -99,7 +101,7 @@ static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
}
static void pl050_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
switch (offset >> 2) {
@ -124,27 +126,18 @@ static void pl050_write(void *opaque, target_phys_addr_t offset,
hw_error("pl050_write: Bad offset %x\n", (int)offset);
}
}
static CPUReadMemoryFunc * const pl050_readfn[] = {
pl050_read,
pl050_read,
pl050_read
};
static CPUWriteMemoryFunc * const pl050_writefn[] = {
pl050_write,
pl050_write,
pl050_write
static const MemoryRegionOps pl050_ops = {
.read = pl050_read,
.write = pl050_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl050_init(SysBusDevice *dev, int is_mouse)
{
pl050_state *s = FROM_SYSBUS(pl050_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(pl050_readfn,
pl050_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl050_ops, s, "pl050", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->is_mouse = is_mouse;
if (s->is_mouse)

27
hw/pl061.c
View File

@ -30,6 +30,7 @@ static const uint8_t pl061_id_luminary[12] =
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t locked;
uint32_t data;
uint32_t old_data;
@ -112,7 +113,8 @@ static void pl061_update(pl061_state *s)
/* FIXME: Implement input interrupts. */
}
static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl061_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
@ -168,7 +170,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
}
static void pl061_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
uint8_t mask;
@ -262,27 +264,18 @@ static void pl061_set_irq(void * opaque, int irq, int level)
}
}
static CPUReadMemoryFunc * const pl061_readfn[] = {
pl061_read,
pl061_read,
pl061_read
};
static CPUWriteMemoryFunc * const pl061_writefn[] = {
pl061_write,
pl061_write,
pl061_write
static const MemoryRegionOps pl061_ops = {
.read = pl061_read,
.write = pl061_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl061_init(SysBusDevice *dev, const unsigned char *id)
{
int iomemtype;
pl061_state *s = FROM_SYSBUS(pl061_state, dev);
s->id = id;
iomemtype = cpu_register_io_memory(pl061_readfn,
pl061_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl061_ops, s, "pl061", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
qdev_init_gpio_out(&dev->qdev, s->out, 8);

27
hw/pl080.c
View File

@ -37,6 +37,7 @@ typedef struct {
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
uint8_t tc_int;
uint8_t tc_mask;
uint8_t err_int;
@ -217,7 +218,8 @@ again:
}
}
static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl080_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
uint32_t i;
@ -285,7 +287,7 @@ static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
}
static void pl080_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
int i;
@ -344,27 +346,18 @@ static void pl080_write(void *opaque, target_phys_addr_t offset,
pl080_update(s);
}
static CPUReadMemoryFunc * const pl080_readfn[] = {
pl080_read,
pl080_read,
pl080_read
};
static CPUWriteMemoryFunc * const pl080_writefn[] = {
pl080_write,
pl080_write,
pl080_write
static const MemoryRegionOps pl080_ops = {
.read = pl080_read,
.write = pl080_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl08x_init(SysBusDevice *dev, int nchannels)
{
int iomemtype;
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
iomemtype = cpu_register_io_memory(pl080_readfn,
pl080_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl080_ops, s, "pl080", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->nchannels = nchannels;
return 0;

27
hw/pl110.c
View File

@ -40,6 +40,7 @@ enum pl110_version
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
DisplayState *ds;
int version;
@ -301,7 +302,8 @@ static void pl110_update(pl110_state *s)
/* TODO: Implement interrupts. */
}
static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
@ -350,7 +352,7 @@ static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
}
static void pl110_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
uint64_t val, unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
int n;
@ -416,16 +418,10 @@ static void pl110_write(void *opaque, target_phys_addr_t offset,
}
}
static CPUReadMemoryFunc * const pl110_readfn[] = {
pl110_read,
pl110_read,
pl110_read
};
static CPUWriteMemoryFunc * const pl110_writefn[] = {
pl110_write,
pl110_write,
pl110_write
static const MemoryRegionOps pl110_ops = {
.read = pl110_read,
.write = pl110_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void pl110_mux_ctrl_set(void *opaque, int line, int level)
@ -437,12 +433,9 @@ static void pl110_mux_ctrl_set(void *opaque, int line, int level)
static int pl110_init(SysBusDevice *dev)
{
pl110_state *s = FROM_SYSBUS(pl110_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(pl110_readfn,
pl110_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
s->ds = graphic_console_init(pl110_update_display,

26
hw/pl181.c
View File

@ -24,6 +24,7 @@ do { printf("pl181: " fmt , ## __VA_ARGS__); } while (0)
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
SDState *card;
uint32_t clock;
uint32_t power;
@ -259,7 +260,8 @@ static void pl181_fifo_run(pl181_state *s)
}
}
static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl181_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
uint32_t tmp;
@ -342,7 +344,7 @@ static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
}
static void pl181_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
@ -412,16 +414,10 @@ static void pl181_write(void *opaque, target_phys_addr_t offset,
pl181_update(s);
}
static CPUReadMemoryFunc * const pl181_readfn[] = {
pl181_read,
pl181_read,
pl181_read
};
static CPUWriteMemoryFunc * const pl181_writefn[] = {
pl181_write,
pl181_write,
pl181_write
static const MemoryRegionOps pl181_ops = {
.read = pl181_read,
.write = pl181_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void pl181_reset(void *opaque)
@ -453,13 +449,11 @@ static void pl181_reset(void *opaque)
static int pl181_init(SysBusDevice *dev)
{
int iomemtype;
pl181_state *s = FROM_SYSBUS(pl181_state, dev);
DriveInfo *dinfo;
iomemtype = cpu_register_io_memory(pl181_readfn, pl181_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl181_ops, s, "pl181", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq[0]);
sysbus_init_irq(dev, &s->irq[1]);
qdev_init_gpio_out(&s->busdev.qdev, s->cardstatus, 2);

28
hw/pl190.c
View File

@ -17,6 +17,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t level;
uint32_t soft_level;
uint32_t irq_enable;
@ -84,7 +85,8 @@ static void pl190_update_vectors(pl190_state *s)
pl190_update(s);
}
static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
int i;
@ -140,7 +142,8 @@ static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
}
}
static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
static void pl190_write(void *opaque, target_phys_addr_t offset,
uint64_t val, unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
@ -199,16 +202,10 @@ static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
pl190_update(s);
}
static CPUReadMemoryFunc * const pl190_readfn[] = {
pl190_read,
pl190_read,
pl190_read
};
static CPUWriteMemoryFunc * const pl190_writefn[] = {
pl190_write,
pl190_write,
pl190_write
static const MemoryRegionOps pl190_ops = {
.read = pl190_read,
.write = pl190_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void pl190_reset(DeviceState *d)
@ -230,12 +227,9 @@ static void pl190_reset(DeviceState *d)
static int pl190_init(SysBusDevice *dev)
{
pl190_state *s = FROM_SYSBUS(pl190_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(pl190_readfn,
pl190_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
memory_region_init_io(&s->iomem, &pl190_ops, s, "pl190", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->fiq);

68
hw/ppc4xx_pci.c
View File

@ -54,6 +54,8 @@ struct PPC4xxPCIState {
PCIHostState pci_state;
PCIDevice *pci_dev;
MemoryRegion iomem_addr;
MemoryRegion iomem_regs;
};
typedef struct PPC4xxPCIState PPC4xxPCIState;
@ -84,35 +86,30 @@ typedef struct PPC4xxPCIState PPC4xxPCIState;
#define PCI_REG_SIZE 0x40
static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
return ppc4xx_pci->pci_state.config_reg;
}
static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
&pci4xx_cfgaddr_readl,
&pci4xx_cfgaddr_readl,
&pci4xx_cfgaddr_readl,
};
static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
ppc4xx_pci->pci_state.config_reg = value & ~0x3;
}
static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
&pci4xx_cfgaddr_writel,
&pci4xx_cfgaddr_writel,
&pci4xx_cfgaddr_writel,
static const MemoryRegionOps pci4xx_cfgaddr_ops = {
.read = pci4xx_cfgaddr_read,
.write = pci4xx_cfgaddr_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
@ -179,7 +176,8 @@ static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
}
}
static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
uint32_t value;
@ -246,16 +244,10 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
return value;
}
static CPUReadMemoryFunc * const pci_reg_read[] = {
&ppc4xx_pci_reg_read4,
&ppc4xx_pci_reg_read4,
&ppc4xx_pci_reg_read4,
};
static CPUWriteMemoryFunc * const pci_reg_write[] = {
&ppc4xx_pci_reg_write4,
&ppc4xx_pci_reg_write4,
&ppc4xx_pci_reg_write4,
static const MemoryRegionOps pci_reg_ops = {
.read = ppc4xx_pci_reg_read4,
.write = ppc4xx_pci_reg_write4,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void ppc4xx_pci_reset(void *opaque)
@ -337,7 +329,6 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
target_phys_addr_t registers)
{
PPC4xxPCIState *controller;
int index;
static int ppc4xx_pci_id;
uint8_t *pci_conf;
@ -360,12 +351,11 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
/* CFGADDR */
index = cpu_register_io_memory(pci4xx_cfgaddr_read,
pci4xx_cfgaddr_write, controller,
DEVICE_LITTLE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
memory_region_init_io(&controller->iomem_addr, &pci4xx_cfgaddr_ops,
controller, "pci.cfgaddr", 4);
memory_region_add_subregion(get_system_memory(),
config_space + PCIC0_CFGADDR,
&controller->iomem_addr);
/* CFGDATA */
memory_region_init_io(&controller->pci_state.data_mem,
@ -376,11 +366,10 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
&controller->pci_state.data_mem);
/* Internal registers */
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
DEVICE_LITTLE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
memory_region_init_io(&controller->iomem_regs, &pci_reg_ops, controller,
"pci.regs", PCI_REG_SIZE);
memory_region_add_subregion(get_system_memory(), registers,
&controller->iomem_regs);
qemu_register_reset(ppc4xx_pci_reset, controller);
@ -389,9 +378,4 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
&vmstate_ppc4xx_pci, controller);
return controller->pci_state.bus;
free:
printf("%s error\n", __func__);
g_free(controller);
return NULL;
}

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