xqemu/hw/xtensa/Makefile.objs

obj-y += mx_pic.o
obj-y += pic_cpu.o
obj-y += sim.o
obj-y += xtensa_memory.o
obj-y += xtfpga.o
target/xtensa: add MX interrupt controller MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2013-02-17 12:38:58 +00:00			`obj-y += mx_pic.o`
hw: move boards and other isolated files to hw/ARCH Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2013-02-05 11:03:15 +00:00			`obj-y += pic_cpu.o`
hw/xtensa: remove extraneous xtensa_ prefix from file names While at it rename lx60 (named after the first board of the family) to more generic xtfpga (the family name). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2014-06-21 06:39:58 +00:00			`obj-y += sim.o`
hw/xtensa: extract xtensa_create_memory_regions XTFPGA boards should populate core memory regions the same way sim machine does. Move xtensa_create_memory_regions implementation to a separate file and use it to create instruction and data memory regions on XTFPGA boards. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2017-12-22 21:53:36 +00:00			`obj-y += xtensa_memory.o`
hw/xtensa: remove extraneous xtensa_ prefix from file names While at it rename lx60 (named after the first board of the family) to more generic xtfpga (the family name). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2014-06-21 06:39:58 +00:00			`obj-y += xtfpga.o`