mirror of https://github.com/xqemu/xqemu.git
108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*
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* Copyright (C) 2015 Imagination Technologies
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/misc/mips_cmgcr.h"
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/* Read GCR registers */
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static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
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{
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MIPSGCRState *gcr = (MIPSGCRState *) opaque;
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switch (addr) {
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/* Global Control Block Register */
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case GCR_CONFIG_OFS:
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/* Set PCORES to 0 */
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return 0;
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case GCR_BASE_OFS:
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return gcr->gcr_base;
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case GCR_REV_OFS:
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return gcr->gcr_rev;
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case GCR_L2_CONFIG_OFS:
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/* L2 BYPASS */
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return GCR_L2_CONFIG_BYPASS_MSK;
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/* Core-Local and Core-Other Control Blocks */
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case MIPS_CLCB_OFS + GCR_CL_CONFIG_OFS:
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case MIPS_COCB_OFS + GCR_CL_CONFIG_OFS:
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/* Set PVP to # of VPs - 1 */
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return gcr->num_vps - 1;
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case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS:
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return 0;
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default:
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qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx
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"\n", size, addr);
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return 0;
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}
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return 0;
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}
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/* Write GCR registers */
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static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
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{
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switch (addr) {
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default:
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qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx
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" 0x%" PRIx64 "\n", size, addr, data);
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break;
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}
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}
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static const MemoryRegionOps gcr_ops = {
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.read = gcr_read,
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.write = gcr_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.max_access_size = 8,
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},
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};
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static void mips_gcr_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSGCRState *s = MIPS_GCR(obj);
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memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s,
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"mips-gcr", GCR_ADDRSPACE_SZ);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static Property mips_gcr_properties[] = {
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DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
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DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
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DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mips_gcr_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = mips_gcr_properties;
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}
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static const TypeInfo mips_gcr_info = {
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.name = TYPE_MIPS_GCR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MIPSGCRState),
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.instance_init = mips_gcr_init,
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.class_init = mips_gcr_class_init,
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};
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static void mips_gcr_register_types(void)
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{
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type_register_static(&mips_gcr_info);
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}
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type_init(mips_gcr_register_types)
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