From ffe9fad6857039b242c0387fccfaebedb73822e8 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Sun, 11 Jan 2015 13:11:13 -0800
Subject: [PATCH] Minor tweaks while reviewing instructions.

---
 src/alloy/backend/x64/x64_sequences.cc | 2 ++
 src/alloy/frontend/ppc/ppc_emit_alu.cc | 9 ++++-----
 src/alloy/frontend/ppc/ppc_emit_fpu.cc | 3 +++
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/alloy/backend/x64/x64_sequences.cc b/src/alloy/backend/x64/x64_sequences.cc
index 8a1467a43..81803d8c2 100644
--- a/src/alloy/backend/x64/x64_sequences.cc
+++ b/src/alloy/backend/x64/x64_sequences.cc
@@ -2893,6 +2893,8 @@ EMITTER(VECTOR_ADD, MATCH(I<OPCODE_VECTOR_ADD, V128<>, V128<>, V128<>>)){
             }
             break;
           case FLOAT32_TYPE:
+            assert_false(is_unsigned);
+            assert_false(saturate);
             e.vaddps(dest, src1, src2);
             break;
           default: assert_unhandled_case(part_type); break;
diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/alloy/frontend/ppc/ppc_emit_alu.cc
index 93d1b4156..94af993ba 100644
--- a/src/alloy/frontend/ppc/ppc_emit_alu.cc
+++ b/src/alloy/frontend/ppc/ppc_emit_alu.cc
@@ -365,9 +365,9 @@ XEEMITTER(mullwx, 0x7C0001D6, XO)(PPCHIRBuilder& f, InstrData& i) {
     XEINSTRNOTIMPLEMENTED();
     return 1;
   }
-  Value* v = f.Mul(
-      f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE),
-      f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE));
+  Value* v = f.SignExtend(f.Mul(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE),
+                                f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE)),
+                          INT64_TYPE);
   f.StoreGPR(i.XO.RT, v);
   if (i.XO.Rc) {
     f.UpdateCR(0, v);
@@ -743,8 +743,7 @@ XEEMITTER(nandx, 0x7C0003B8, X)(PPCHIRBuilder& f, InstrData& i) {
 
 XEEMITTER(norx, 0x7C0000F8, X)(PPCHIRBuilder& f, InstrData& i) {
   // RA <- ¬((RS) | (RB))
-  Value* ra = f.Or(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB));
-  ra = f.Not(ra);
+  Value* ra = f.Not(f.Or(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB)));
   f.StoreGPR(i.X.RA, ra);
   if (i.X.Rc) {
     f.UpdateCR(0, ra);
diff --git a/src/alloy/frontend/ppc/ppc_emit_fpu.cc b/src/alloy/frontend/ppc/ppc_emit_fpu.cc
index 43945f8af..750054347 100644
--- a/src/alloy/frontend/ppc/ppc_emit_fpu.cc
+++ b/src/alloy/frontend/ppc/ppc_emit_fpu.cc
@@ -454,6 +454,9 @@ XEEMITTER(mtfsfx, 0xFC00058E, XFL)(PPCHIRBuilder& f, InstrData& i) {
     return 1;
   } else {
     // Directly store.
+    // TODO(benvanik): use w/field mask to select bits.
+    i.XFL.W;
+    i.XFL.FM;
     f.StoreFPSCR(f.Cast(f.LoadFPR(i.XFL.RB), INT64_TYPE));
   }
   return 0;