Shift tests and fix for bad sradi decoding.
This commit is contained in:
Ben Vanik
parent
8666c3975a
commit
feffe590f2
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@ -1112,13 +1112,17 @@ XEEMITTER(sradix, 0x7C000674, XS)(PPCHIRBuilder& f, InstrData& i) {
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// CA is set if any bits are shifted out of the right and if the result
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// is negative.
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assert_true(sh);
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uint64_t mask = XEMASK(64 - sh, 63);
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Value* ca = f.And(f.Truncate(f.Shr(v, 63), INT8_TYPE),
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f.IsTrue(f.And(v, f.LoadConstant(mask))));
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f.StoreCA(ca);
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if (sh) {
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uint64_t mask = XEMASK(64 - sh, 63);
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Value* ca = f.And(f.Truncate(f.Shr(v, 63), INT8_TYPE),
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f.IsTrue(f.And(v, f.LoadConstant(mask))));
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f.StoreCA(ca);
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v = f.Sha(v, sh);
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} else {
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f.StoreCA(f.LoadZero(INT8_TYPE));
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}
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v = f.Sha(v, sh);
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f.StoreGPR(i.XS.RA, v);
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if (i.XS.Rc) {
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f.UpdateCR(0, v);
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@ -1252,6 +1256,7 @@ void RegisterEmitCategoryALU() {
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XEREGISTERINSTR(srwx, 0x7C000430);
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XEREGISTERINSTR(sradx, 0x7C000634);
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XEREGISTERINSTR(sradix, 0x7C000674);
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XEREGISTERINSTR(sradix, 0x7C000676); // HACK
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XEREGISTERINSTR(srawx, 0x7C000630);
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XEREGISTERINSTR(srawix, 0x7C000670);
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}
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@ -591,7 +591,11 @@ static InstrType instr_table_31_unprep[] = {
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INSTRUCTION(srawix, 0x7C000670, X, General, srawix,
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"Shift Right Algebraic Word Immediate"),
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INSTRUCTION(sradix, 0x7C000674, XS, General, sradix,
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"Shift Right Algebraic Doubleword Immediate"), // TODO
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"Shift Right Algebraic Doubleword Immediate"),
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INSTRUCTION(sradix, 0x7C000674, XS, General, sradix,
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"Shift Right Algebraic Doubleword Immediate"),
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INSTRUCTION(sradix, 0x7C000676, XS, General, sradix,
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"Shift Right Algebraic Doubleword Immediate"), // HACK
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INSTRUCTION(eieio, 0x7C0006AC, X, General, _,
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"Enforce In-Order Execution of I/O Instruction"),
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INSTRUCTION(sthbrx, 0x7C00072C, X, General, X_RT_RA0_RB,
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Binary file not shown.
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@ -4,6 +4,10 @@
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Disassembly of section .text:
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0000000000100000 <test_ori>:
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0000000000100000 <test_ori_1>:
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100000: 60 83 fe dc ori r3,r4,65244
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100004: 4e 80 00 20 blr
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0000000000100008 <test_ori_2>:
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100008: 60 83 fe dc ori r3,r4,65244
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10000c: 4e 80 00 20 blr
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@ -1 +1,2 @@
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0000000000000000 t test_ori
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0000000000000000 t test_ori_1
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0000000000000008 t test_ori_2
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Binary file not shown.
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@ -0,0 +1,33 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_sld.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_sld_1>:
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100000: 7c 83 28 36 sld r3,r4,r5
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100004: 4e 80 00 20 blr
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0000000000100008 <test_sld_2>:
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100008: 7c 83 28 36 sld r3,r4,r5
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_sld_3>:
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100010: 7c 83 28 36 sld r3,r4,r5
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100014: 4e 80 00 20 blr
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0000000000100018 <test_sld_4>:
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100018: 7c 83 28 36 sld r3,r4,r5
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10001c: 4e 80 00 20 blr
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0000000000100020 <test_sld_5>:
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100020: 7c 83 28 36 sld r3,r4,r5
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100024: 4e 80 00 20 blr
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0000000000100028 <test_sld_6>:
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100028: 7c 83 28 36 sld r3,r4,r5
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_sld_7>:
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100030: 7c 83 28 36 sld r3,r4,r5
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100034: 4e 80 00 20 blr
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@ -0,0 +1,7 @@
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0000000000000000 t test_sld_1
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0000000000000008 t test_sld_2
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0000000000000010 t test_sld_3
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0000000000000018 t test_sld_4
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0000000000000020 t test_sld_5
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0000000000000028 t test_sld_6
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0000000000000030 t test_sld_7
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Binary file not shown.
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@ -0,0 +1,41 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_slw.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_slw_1>:
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100000: 7c 83 28 30 slw r3,r4,r5
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100004: 4e 80 00 20 blr
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0000000000100008 <test_slw_2>:
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100008: 7c 83 28 30 slw r3,r4,r5
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_slw_3>:
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100010: 7c 83 28 30 slw r3,r4,r5
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100014: 4e 80 00 20 blr
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0000000000100018 <test_slw_4>:
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100018: 7c 83 28 30 slw r3,r4,r5
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10001c: 4e 80 00 20 blr
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0000000000100020 <test_slw_5>:
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100020: 7c 83 28 30 slw r3,r4,r5
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100024: 4e 80 00 20 blr
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0000000000100028 <test_slw_6>:
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100028: 7c 83 28 30 slw r3,r4,r5
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_slw_7>:
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100030: 7c 83 28 30 slw r3,r4,r5
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100034: 4e 80 00 20 blr
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0000000000100038 <test_slw_8>:
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100038: 7c 83 28 30 slw r3,r4,r5
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10003c: 4e 80 00 20 blr
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0000000000100040 <test_slw_9>:
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100040: 7c 83 28 30 slw r3,r4,r5
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100044: 4e 80 00 20 blr
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@ -0,0 +1,9 @@
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0000000000000000 t test_slw_1
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0000000000000008 t test_slw_2
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0000000000000010 t test_slw_3
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0000000000000018 t test_slw_4
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0000000000000020 t test_slw_5
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0000000000000028 t test_slw_6
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0000000000000030 t test_slw_7
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0000000000000038 t test_slw_8
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0000000000000040 t test_slw_9
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Binary file not shown.
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@ -0,0 +1,40 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_srad.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_srad_1>:
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100000: 7c 83 2e 34 srad r3,r4,r5
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_srad_2>:
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10000c: 7c 83 2e 34 srad r3,r4,r5
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100010: 7c c0 01 14 adde r6,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_srad_3>:
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100018: 7c 83 2e 34 srad r3,r4,r5
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_srad_4>:
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100024: 7c 83 2e 34 srad r3,r4,r5
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_srad_5>:
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100030: 7c 83 2e 34 srad r3,r4,r5
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100034: 7c c0 01 14 adde r6,r0,r0
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100038: 4e 80 00 20 blr
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000000000010003c <test_srad_6>:
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10003c: 7c 83 2e 34 srad r3,r4,r5
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100040: 7c c0 01 14 adde r6,r0,r0
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100044: 4e 80 00 20 blr
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0000000000100048 <test_srad_7>:
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100048: 7c 83 2e 34 srad r3,r4,r5
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10004c: 7c c0 01 14 adde r6,r0,r0
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100050: 4e 80 00 20 blr
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@ -0,0 +1,7 @@
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0000000000000000 t test_srad_1
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000000000000000c t test_srad_2
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0000000000000018 t test_srad_3
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0000000000000024 t test_srad_4
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0000000000000030 t test_srad_5
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000000000000003c t test_srad_6
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0000000000000048 t test_srad_7
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Binary file not shown.
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@ -0,0 +1,30 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_sradi.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_sradi_1>:
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100000: 7c 83 06 74 sradi r3,r4,0
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_sradi_2>:
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10000c: 7c 83 06 74 sradi r3,r4,0
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100010: 7c c0 01 14 adde r6,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_sradi_3>:
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100018: 7c 83 0e 74 sradi r3,r4,1
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_sradi_4>:
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100024: 7c 83 f6 76 sradi r3,r4,62
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_sradi_5>:
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100030: 7c 83 fe 76 sradi r3,r4,63
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100034: 7c c0 01 14 adde r6,r0,r0
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100038: 4e 80 00 20 blr
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@ -0,0 +1,5 @@
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0000000000000000 t test_sradi_1
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000000000000000c t test_sradi_2
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0000000000000018 t test_sradi_3
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0000000000000024 t test_sradi_4
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0000000000000030 t test_sradi_5
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Binary file not shown.
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@ -0,0 +1,50 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_sraw.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_sraw_1>:
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100000: 7c 83 2e 30 sraw r3,r4,r5
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_sraw_2>:
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10000c: 7c 83 2e 30 sraw r3,r4,r5
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100010: 7c c0 01 14 adde r6,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_sraw_3>:
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100018: 7c 83 2e 30 sraw r3,r4,r5
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_sraw_4>:
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100024: 7c 83 2e 30 sraw r3,r4,r5
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_sraw_5>:
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100030: 7c 83 2e 30 sraw r3,r4,r5
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100034: 7c c0 01 14 adde r6,r0,r0
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100038: 4e 80 00 20 blr
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000000000010003c <test_sraw_6>:
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10003c: 7c 83 2e 30 sraw r3,r4,r5
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100040: 7c c0 01 14 adde r6,r0,r0
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100044: 4e 80 00 20 blr
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0000000000100048 <test_sraw_7>:
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100048: 7c 83 2e 30 sraw r3,r4,r5
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10004c: 7c c0 01 14 adde r6,r0,r0
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100050: 4e 80 00 20 blr
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0000000000100054 <test_sraw_8>:
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100054: 7c 83 2e 30 sraw r3,r4,r5
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100058: 7c c0 01 14 adde r6,r0,r0
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10005c: 4e 80 00 20 blr
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0000000000100060 <test_sraw_9>:
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100060: 7c 83 2e 30 sraw r3,r4,r5
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100064: 7c c0 01 14 adde r6,r0,r0
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100068: 4e 80 00 20 blr
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@ -0,0 +1,9 @@
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0000000000000000 t test_sraw_1
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000000000000000c t test_sraw_2
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0000000000000018 t test_sraw_3
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0000000000000024 t test_sraw_4
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0000000000000030 t test_sraw_5
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000000000000003c t test_sraw_6
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0000000000000048 t test_sraw_7
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0000000000000054 t test_sraw_8
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0000000000000060 t test_sraw_9
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Binary file not shown.
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@ -0,0 +1,30 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_srawi.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_srawi_1>:
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100000: 7c 83 06 70 srawi r3,r4,0
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_srawi_2>:
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10000c: 7c 83 06 70 srawi r3,r4,0
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100010: 7c c0 01 14 adde r6,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_srawi_3>:
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100018: 7c 83 0e 70 srawi r3,r4,1
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_srawi_4>:
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100024: 7c 83 f6 70 srawi r3,r4,30
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_srawi_5>:
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100030: 7c 83 fe 70 srawi r3,r4,31
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100034: 7c c0 01 14 adde r6,r0,r0
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100038: 4e 80 00 20 blr
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@ -0,0 +1,5 @@
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0000000000000000 t test_srawi_1
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000000000000000c t test_srawi_2
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0000000000000018 t test_srawi_3
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0000000000000024 t test_srawi_4
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0000000000000030 t test_srawi_5
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Binary file not shown.
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@ -0,0 +1,33 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_srd.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_srd_1>:
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100000: 7c 83 2c 36 srd r3,r4,r5
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100004: 4e 80 00 20 blr
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0000000000100008 <test_srd_2>:
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100008: 7c 83 2c 36 srd r3,r4,r5
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_srd_3>:
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100010: 7c 83 2c 36 srd r3,r4,r5
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100014: 4e 80 00 20 blr
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0000000000100018 <test_srd_4>:
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100018: 7c 83 2c 36 srd r3,r4,r5
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10001c: 4e 80 00 20 blr
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0000000000100020 <test_srd_5>:
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100020: 7c 83 2c 36 srd r3,r4,r5
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100024: 4e 80 00 20 blr
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0000000000100028 <test_srd_6>:
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100028: 7c 83 2c 36 srd r3,r4,r5
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_srd_7>:
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100030: 7c 83 2c 36 srd r3,r4,r5
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100034: 4e 80 00 20 blr
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0000000000000000 t test_srd_1
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0000000000000008 t test_srd_2
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0000000000000010 t test_srd_3
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0000000000000018 t test_srd_4
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0000000000000020 t test_srd_5
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0000000000000028 t test_srd_6
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0000000000000030 t test_srd_7
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Binary file not shown.
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_srw.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_srw_1>:
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100000: 7c 83 2c 30 srw r3,r4,r5
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100004: 4e 80 00 20 blr
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0000000000100008 <test_srw_2>:
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100008: 7c 83 2c 30 srw r3,r4,r5
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_srw_3>:
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100010: 7c 83 2c 30 srw r3,r4,r5
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100014: 4e 80 00 20 blr
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0000000000100018 <test_srw_4>:
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100018: 7c 83 2c 30 srw r3,r4,r5
|
||||
10001c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100020 <test_srw_5>:
|
||||
100020: 7c 83 2c 30 srw r3,r4,r5
|
||||
100024: 4e 80 00 20 blr
|
||||
|
||||
0000000000100028 <test_srw_6>:
|
||||
100028: 7c 83 2c 30 srw r3,r4,r5
|
||||
10002c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100030 <test_srw_7>:
|
||||
100030: 7c 83 2c 30 srw r3,r4,r5
|
||||
100034: 4e 80 00 20 blr
|
||||
|
||||
0000000000100038 <test_srw_8>:
|
||||
100038: 7c 83 2c 30 srw r3,r4,r5
|
||||
10003c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100040 <test_srw_9>:
|
||||
100040: 7c 83 2c 30 srw r3,r4,r5
|
||||
100044: 4e 80 00 20 blr
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
0000000000000000 t test_srw_1
|
||||
0000000000000008 t test_srw_2
|
||||
0000000000000010 t test_srw_3
|
||||
0000000000000018 t test_srw_4
|
||||
0000000000000020 t test_srw_5
|
||||
0000000000000028 t test_srw_6
|
||||
0000000000000030 t test_srw_7
|
||||
0000000000000038 t test_srw_8
|
||||
0000000000000040 t test_srw_9
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
test_ori:
|
||||
test_ori_1:
|
||||
#_ REGISTER_IN r4 0xDEADBEEF00000000
|
||||
|
||||
ori r3, r4, 0xFEDC
|
||||
|
|
@ -6,3 +6,12 @@ test_ori:
|
|||
blr
|
||||
#_ REGISTER_OUT r3 0xDEADBEEF0000FEDC
|
||||
#_ REGISTER_OUT r4 0xDEADBEEF00000000
|
||||
|
||||
test_ori_2:
|
||||
#_ REGISTER_IN r4 0xDEADBEEF10000000
|
||||
|
||||
ori r3, r4, 0xFEDC
|
||||
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xDEADBEEF1000FEDC
|
||||
#_ REGISTER_OUT r4 0xDEADBEEF10000000
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
test_sld_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 0
|
||||
sld r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_sld_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
sld r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_sld_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
sld r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
|
||||
test_sld_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 62
|
||||
sld r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xc000000000000000
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 62
|
||||
|
||||
test_sld_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 63
|
||||
sld r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x8000000000000000
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 63
|
||||
|
||||
test_sld_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 64
|
||||
sld r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 64
|
||||
|
||||
test_sld_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 100
|
||||
sld r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 100
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
test_slw_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 0
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_slw_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_slw_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
|
||||
test_slw_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 63
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 63
|
||||
|
||||
test_slw_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 64
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 64
|
||||
|
||||
test_slw_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 100
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 100
|
||||
|
||||
test_slw_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 30
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x00000000c0000000
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 30
|
||||
|
||||
test_slw_8:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 31
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x0000000080000000
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 31
|
||||
|
||||
test_slw_9:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 32
|
||||
slw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 32
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
test_srad_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 0
|
||||
srad r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_srad_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
srad r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_srad_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
srad r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_srad_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 62
|
||||
srad r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 62
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_srad_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 63
|
||||
srad r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 63
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_srad_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 64
|
||||
srad r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 64
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_srad_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 100
|
||||
srad r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 100
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
test_sradi_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
sradi r3, r4, 0
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_sradi_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
sradi r3, r4, 0
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_sradi_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
sradi r3, r4, 1
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_sradi_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
sradi r3, r4, 62
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_sradi_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
sradi r3, r4, 63
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
test_sraw_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 0
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_sraw_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_sraw_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_sraw_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 63
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 63
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_sraw_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 64
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 64
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_sraw_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 100
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 100
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_sraw_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 30
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 30
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_sraw_8:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 31
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 31
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_sraw_9:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 32
|
||||
sraw r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 32
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
test_srawi_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
srawi r3, r4, 0
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_srawi_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
srawi r3, r4, 0
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_srawi_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
srawi r3, r4, 1
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_srawi_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
srawi r3, r4, 30
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_srawi_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
srawi r3, r4, 31
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
test_srd_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 0
|
||||
srd r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_srd_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
srd r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_srd_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
srd r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
|
||||
test_srd_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 62
|
||||
srd r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x0000000000000003
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 62
|
||||
|
||||
test_srd_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 63
|
||||
srd r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x0000000000000001
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 63
|
||||
|
||||
test_srd_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 64
|
||||
srd r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 64
|
||||
|
||||
test_srd_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 100
|
||||
srd r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 100
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
test_srw_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 0
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_srw_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
|
||||
test_srw_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x000000007FFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
|
||||
test_srw_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 63
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 63
|
||||
|
||||
test_srw_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 64
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 64
|
||||
|
||||
test_srw_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 100
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 100
|
||||
|
||||
test_srw_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 30
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x0000000000000003
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 30
|
||||
|
||||
test_srw_8:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 31
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x0000000000000001
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 31
|
||||
|
||||
test_srw_9:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 32
|
||||
srw r3, r4, r5
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 32
|
||||
Loading…
Reference in New Issue