Subtract instruction tests.

src/alloy/frontend/ppc/test/bin/instr_subf.dis

@@ -0,0 +1,25 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subf.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_subf_1>:
+  100000:	7c 6a 58 50 	subf    r3,r10,r11
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_subf_2>:
+  100008:	7c 6a 58 50 	subf    r3,r10,r11
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_subf_3>:
+  100010:	7c 6a 58 50 	subf    r3,r10,r11
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_subf_4>:
+  100018:	7c 6a 58 50 	subf    r3,r10,r11
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_subf_5>:
+  100020:	7c 6a 58 50 	subf    r3,r10,r11
+  100024:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_subf.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_subf_1
+0000000000000008 t test_subf_2
+0000000000000010 t test_subf_3
+0000000000000018 t test_subf_4
+0000000000000020 t test_subf_5

src/alloy/frontend/ppc/test/bin/instr_subfc.dis

@@ -0,0 +1,30 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfc.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_subfc_1>:
+  100000:	7c 6a 58 10 	subfc   r3,r10,r11
+  100004:	7c 80 01 14 	adde    r4,r0,r0
+  100008:	4e 80 00 20 	blr
+
+000000000010000c <test_subfc_2>:
+  10000c:	7c 6a 58 10 	subfc   r3,r10,r11
+  100010:	7c 80 01 14 	adde    r4,r0,r0
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_subfc_3>:
+  100018:	7c 6a 58 10 	subfc   r3,r10,r11
+  10001c:	7c 80 01 14 	adde    r4,r0,r0
+  100020:	4e 80 00 20 	blr
+
+0000000000100024 <test_subfc_4>:
+  100024:	7c 6a 58 10 	subfc   r3,r10,r11
+  100028:	7c 80 01 14 	adde    r4,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_subfc_5>:
+  100030:	7c 6a 58 10 	subfc   r3,r10,r11
+  100034:	7c 80 01 14 	adde    r4,r0,r0
+  100038:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_subfc.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_subfc_1
+000000000000000c t test_subfc_2
+0000000000000018 t test_subfc_3
+0000000000000024 t test_subfc_4
+0000000000000030 t test_subfc_5

src/alloy/frontend/ppc/test/bin/instr_subfe.dis

@@ -4,22 +4,27 @@
 
 Disassembly of section .text:
 
-0000000000100000 <test_subfe>:
+0000000000100000 <test_subfe_1>:
   100000:	7c 6a 59 10 	subfe   r3,r10,r11
-  100004:	4e 80 00 20 	blr
+  100004:	7c 80 01 14 	adde    r4,r0,r0
+  100008:	4e 80 00 20 	blr
 
-0000000000100008 <test_subfe_2>:
+000000000010000c <test_subfe_2>:
-  100008:	7c 6a 59 10 	subfe   r3,r10,r11
+  10000c:	7c 6a 59 10 	subfe   r3,r10,r11
-  10000c:	4e 80 00 20 	blr
+  100010:	7c 80 01 14 	adde    r4,r0,r0
-
-0000000000100010 <test_subfe_3>:
-  100010:	7c 6a 59 10 	subfe   r3,r10,r11
   100014:	4e 80 00 20 	blr
 
-0000000000100018 <test_subfe_4>:
+0000000000100018 <test_subfe_3>:
   100018:	7c 6a 59 10 	subfe   r3,r10,r11
-  10001c:	4e 80 00 20 	blr
+  10001c:	7c 80 01 14 	adde    r4,r0,r0
+  100020:	4e 80 00 20 	blr
 
-0000000000100020 <test_subfe_5>:
+0000000000100024 <test_subfe_4>:
-  100020:	7c 6a 59 10 	subfe   r3,r10,r11
+  100024:	7c 6a 59 10 	subfe   r3,r10,r11
-  100024:	4e 80 00 20 	blr
+  100028:	7c 80 01 14 	adde    r4,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_subfe_5>:
+  100030:	7c 6a 59 10 	subfe   r3,r10,r11
+  100034:	7c 80 01 14 	adde    r4,r0,r0
+  100038:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_subfe.map

@@ -1,5 +1,5 @@
-0000000000000000 t test_subfe
+0000000000000000 t test_subfe_1
-0000000000000008 t test_subfe_2
+000000000000000c t test_subfe_2
-0000000000000010 t test_subfe_3
+0000000000000018 t test_subfe_3
-0000000000000018 t test_subfe_4
+0000000000000024 t test_subfe_4
-0000000000000020 t test_subfe_5
+0000000000000030 t test_subfe_5

src/alloy/frontend/ppc/test/bin/instr_subfic.dis

@@ -0,0 +1,35 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfic.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_subfic_1>:
+  100000:	20 6a 03 c0 	subfic  r3,r10,960
+  100004:	7c 80 01 14 	adde    r4,r0,r0
+  100008:	4e 80 00 20 	blr
+
+000000000010000c <test_subfic_2>:
+  10000c:	20 6a ff 16 	subfic  r3,r10,-234
+  100010:	7c 80 01 14 	adde    r4,r0,r0
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_subfic_3>:
+  100018:	20 6a 00 00 	subfic  r3,r10,0
+  10001c:	7c 80 01 14 	adde    r4,r0,r0
+  100020:	4e 80 00 20 	blr
+
+0000000000100024 <test_subfic_4>:
+  100024:	20 6a 00 00 	subfic  r3,r10,0
+  100028:	7c 80 01 14 	adde    r4,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_subfic_5>:
+  100030:	20 6a 00 01 	subfic  r3,r10,1
+  100034:	7c 80 01 14 	adde    r4,r0,r0
+  100038:	4e 80 00 20 	blr
+
+000000000010003c <test_subfic_6>:
+  10003c:	20 6a ff ff 	subfic  r3,r10,-1
+  100040:	7c 80 01 14 	adde    r4,r0,r0
+  100044:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_subfic.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_subfic_1
+000000000000000c t test_subfic_2
+0000000000000018 t test_subfic_3
+0000000000000024 t test_subfic_4
+0000000000000030 t test_subfic_5
+000000000000003c t test_subfic_6

src/alloy/frontend/ppc/test/bin/instr_subfme.dis

@@ -0,0 +1,65 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfme.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_subfme_one_ca_1>:
+  100000:	7c 63 1a 78 	xor     r3,r3,r3
+  100004:	7c 63 18 f8 	not     r3,r3
+  100008:	30 63 00 01 	addic   r3,r3,1
+  10000c:	7c 6a 01 d0 	subfme  r3,r10
+  100010:	7c 80 01 14 	adde    r4,r0,r0
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_subfme_one_ca_2>:
+  100018:	7c 63 1a 78 	xor     r3,r3,r3
+  10001c:	7c 63 18 f8 	not     r3,r3
+  100020:	30 63 00 01 	addic   r3,r3,1
+  100024:	7c 6a 01 d0 	subfme  r3,r10
+  100028:	7c 80 01 14 	adde    r4,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_subfme_one_ca_3>:
+  100030:	7c 63 1a 78 	xor     r3,r3,r3
+  100034:	7c 63 18 f8 	not     r3,r3
+  100038:	30 63 00 01 	addic   r3,r3,1
+  10003c:	7c 6a 01 d0 	subfme  r3,r10
+  100040:	7c 80 01 14 	adde    r4,r0,r0
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_subfme_one_ca_4>:
+  100048:	7c 63 1a 78 	xor     r3,r3,r3
+  10004c:	7c 63 18 f8 	not     r3,r3
+  100050:	30 63 00 01 	addic   r3,r3,1
+  100054:	7c 6a 01 d0 	subfme  r3,r10
+  100058:	7c 80 01 14 	adde    r4,r0,r0
+  10005c:	4e 80 00 20 	blr
+
+0000000000100060 <test_subfme_zero_ca_1>:
+  100060:	7c 63 1a 78 	xor     r3,r3,r3
+  100064:	30 63 00 01 	addic   r3,r3,1
+  100068:	7c 6a 01 d0 	subfme  r3,r10
+  10006c:	7c 80 01 14 	adde    r4,r0,r0
+  100070:	4e 80 00 20 	blr
+
+0000000000100074 <test_subfme_zero_ca_2>:
+  100074:	7c 63 1a 78 	xor     r3,r3,r3
+  100078:	30 63 00 01 	addic   r3,r3,1
+  10007c:	7c 6a 01 d0 	subfme  r3,r10
+  100080:	7c 80 01 14 	adde    r4,r0,r0
+  100084:	4e 80 00 20 	blr
+
+0000000000100088 <test_subfme_zero_ca_3>:
+  100088:	7c 63 1a 78 	xor     r3,r3,r3
+  10008c:	30 63 00 01 	addic   r3,r3,1
+  100090:	7c 6a 01 d0 	subfme  r3,r10
+  100094:	7c 80 01 14 	adde    r4,r0,r0
+  100098:	4e 80 00 20 	blr
+
+000000000010009c <test_subfme_zero_ca_4>:
+  10009c:	7c 63 1a 78 	xor     r3,r3,r3
+  1000a0:	30 63 00 01 	addic   r3,r3,1
+  1000a4:	7c 6a 01 d0 	subfme  r3,r10
+  1000a8:	7c 80 01 14 	adde    r4,r0,r0
+  1000ac:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_subfme.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_subfme_one_ca_1
+0000000000000018 t test_subfme_one_ca_2
+0000000000000030 t test_subfme_one_ca_3
+0000000000000048 t test_subfme_one_ca_4
+0000000000000060 t test_subfme_zero_ca_1
+0000000000000074 t test_subfme_zero_ca_2
+0000000000000088 t test_subfme_zero_ca_3
+000000000000009c t test_subfme_zero_ca_4

src/alloy/frontend/ppc/test/bin/instr_subfze.dis

@@ -0,0 +1,65 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfze.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_subfze_one_ca_1>:
+  100000:	7c 63 1a 78 	xor     r3,r3,r3
+  100004:	7c 63 18 f8 	not     r3,r3
+  100008:	30 63 00 01 	addic   r3,r3,1
+  10000c:	7c 6a 01 90 	subfze  r3,r10
+  100010:	7c 80 01 14 	adde    r4,r0,r0
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_subfze_one_ca_2>:
+  100018:	7c 63 1a 78 	xor     r3,r3,r3
+  10001c:	7c 63 18 f8 	not     r3,r3
+  100020:	30 63 00 01 	addic   r3,r3,1
+  100024:	7c 6a 01 90 	subfze  r3,r10
+  100028:	7c 80 01 14 	adde    r4,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_subfze_one_ca_3>:
+  100030:	7c 63 1a 78 	xor     r3,r3,r3
+  100034:	7c 63 18 f8 	not     r3,r3
+  100038:	30 63 00 01 	addic   r3,r3,1
+  10003c:	7c 6a 01 90 	subfze  r3,r10
+  100040:	7c 80 01 14 	adde    r4,r0,r0
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_subfze_one_ca_4>:
+  100048:	7c 63 1a 78 	xor     r3,r3,r3
+  10004c:	7c 63 18 f8 	not     r3,r3
+  100050:	30 63 00 01 	addic   r3,r3,1
+  100054:	7c 6a 01 90 	subfze  r3,r10
+  100058:	7c 80 01 14 	adde    r4,r0,r0
+  10005c:	4e 80 00 20 	blr
+
+0000000000100060 <test_subfze_zero_ca_1>:
+  100060:	7c 63 1a 78 	xor     r3,r3,r3
+  100064:	30 63 00 01 	addic   r3,r3,1
+  100068:	7c 6a 01 90 	subfze  r3,r10
+  10006c:	7c 80 01 14 	adde    r4,r0,r0
+  100070:	4e 80 00 20 	blr
+
+0000000000100074 <test_subfze_zero_ca_2>:
+  100074:	7c 63 1a 78 	xor     r3,r3,r3
+  100078:	30 63 00 01 	addic   r3,r3,1
+  10007c:	7c 6a 01 90 	subfze  r3,r10
+  100080:	7c 80 01 14 	adde    r4,r0,r0
+  100084:	4e 80 00 20 	blr
+
+0000000000100088 <test_subfze_zero_ca_3>:
+  100088:	7c 63 1a 78 	xor     r3,r3,r3
+  10008c:	30 63 00 01 	addic   r3,r3,1
+  100090:	7c 6a 01 90 	subfze  r3,r10
+  100094:	7c 80 01 14 	adde    r4,r0,r0
+  100098:	4e 80 00 20 	blr
+
+000000000010009c <test_subfze_zero_ca_4>:
+  10009c:	7c 63 1a 78 	xor     r3,r3,r3
+  1000a0:	30 63 00 01 	addic   r3,r3,1
+  1000a4:	7c 6a 01 90 	subfze  r3,r10
+  1000a8:	7c 80 01 14 	adde    r4,r0,r0
+  1000ac:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_subfze.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_subfze_one_ca_1
+0000000000000018 t test_subfze_one_ca_2
+0000000000000030 t test_subfze_one_ca_3
+0000000000000048 t test_subfze_one_ca_4
+0000000000000060 t test_subfze_zero_ca_1
+0000000000000074 t test_subfze_zero_ca_2
+0000000000000088 t test_subfze_zero_ca_3
+000000000000009c t test_subfze_zero_ca_4

src/alloy/frontend/ppc/test/instr_subf.s

@@ -0,0 +1,44 @@
+test_subf_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  #_ REGISTER_IN r11 0x00000000000103C0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 0x1
+
+test_subf_2:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0
+
+test_subf_3:
+  #_ REGISTER_IN r10 1
+  #_ REGISTER_IN r11 0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 -1
+
+test_subf_4:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 1
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 1
+
+test_subf_5:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0x0

src/alloy/frontend/ppc/test/instr_subfc.s

@@ -0,0 +1,54 @@
+test_subfc_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  #_ REGISTER_IN r11 0x00000000000103C0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfc_2:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfc_3:
+  #_ REGISTER_IN r10 1
+  #_ REGISTER_IN r11 0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfc_4:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 1
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfc_5:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1

src/alloy/frontend/ppc/test/instr_subfe.s

@@ -1,44 +1,54 @@
-test_subfe:
+test_subfe_1:
   #_ REGISTER_IN r10 0x00000000000103BF
   #_ REGISTER_IN r11 0x00000000000103C0
   subfe r3, r10, r11
+  adde r4, r0, r0
   blr
   #_ REGISTER_OUT r10 0x00000000000103BF
   #_ REGISTER_OUT r11 0x00000000000103C0
   #_ REGISTER_OUT r3 0x0
+  #_ REGISTER_OUT r4 1
 
 test_subfe_2:
   #_ REGISTER_IN r10 0
   #_ REGISTER_IN r11 0
   subfe r3, r10, r11
+  adde r4, r0, r0
   blr
   #_ REGISTER_OUT r10 0
   #_ REGISTER_OUT r11 0
-  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0
 
 test_subfe_3:
   #_ REGISTER_IN r10 1
   #_ REGISTER_IN r11 0
   subfe r3, r10, r11
+  adde r4, r0, r0
   blr
   #_ REGISTER_OUT r10 1
   #_ REGISTER_OUT r11 0
-  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
 
 test_subfe_4:
   #_ REGISTER_IN r10 0
   #_ REGISTER_IN r11 1
   subfe r3, r10, r11
+  adde r4, r0, r0
   blr
   #_ REGISTER_OUT r10 0
   #_ REGISTER_OUT r11 1
   #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
 
 test_subfe_5:
   #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
   #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
   subfe r3, r10, r11
+  adde r4, r0, r0
   blr
   #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
   #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
-  #_ REGISTER_OUT r3 0x0
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0

src/alloy/frontend/ppc/test/instr_subfic.s

@@ -0,0 +1,53 @@
+test_subfic_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  subfic r3, r10, 0x3C0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xffffffffffff0001
+  #_ REGISTER_OUT r4 0
+
+test_subfic_2:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  subfic r3, r10, -234
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefb57
+  #_ REGISTER_OUT r4 1
+
+test_subfic_3:
+  #_ REGISTER_IN r10 0
+  subfic r3, r10, 0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfic_4:
+  #_ REGISTER_IN r10 1
+  subfic r3, r10, 0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfic_5:
+  #_ REGISTER_IN r10 0
+  subfic r3, r10, 1
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfic_6:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  subfic r3, r10, -1
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1

src/alloy/frontend/ppc/test/instr_subfme.s

@@ -0,0 +1,91 @@
+test_subfme_one_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc40
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc3f
+  #_ REGISTER_OUT r4 0
+
+test_subfme_zero_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+
+test_subfme_zero_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffd
+  #_ REGISTER_OUT r4 0
+
+test_subfme_zero_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0

src/alloy/frontend/ppc/test/instr_subfze.s

@@ -0,0 +1,91 @@
+test_subfze_one_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc41
+  #_ REGISTER_OUT r4 0
+
+test_subfze_one_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfze_one_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfze_one_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0x1
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc40
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0