Subtract instruction tests.
This commit is contained in:
Ben Vanik
parent
5ba0986155
commit
fdaee413e2
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subf.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_subf_1>:
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100000: 7c 6a 58 50 subf r3,r10,r11
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100004: 4e 80 00 20 blr
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0000000000100008 <test_subf_2>:
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100008: 7c 6a 58 50 subf r3,r10,r11
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_subf_3>:
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100010: 7c 6a 58 50 subf r3,r10,r11
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100014: 4e 80 00 20 blr
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0000000000100018 <test_subf_4>:
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100018: 7c 6a 58 50 subf r3,r10,r11
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10001c: 4e 80 00 20 blr
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0000000000100020 <test_subf_5>:
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100020: 7c 6a 58 50 subf r3,r10,r11
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100024: 4e 80 00 20 blr
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@ -0,0 +1,5 @@
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0000000000000000 t test_subf_1
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0000000000000008 t test_subf_2
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0000000000000010 t test_subf_3
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0000000000000018 t test_subf_4
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0000000000000020 t test_subf_5
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@ -0,0 +1,30 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfc.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_subfc_1>:
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100000: 7c 6a 58 10 subfc r3,r10,r11
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100004: 7c 80 01 14 adde r4,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_subfc_2>:
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10000c: 7c 6a 58 10 subfc r3,r10,r11
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100010: 7c 80 01 14 adde r4,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_subfc_3>:
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100018: 7c 6a 58 10 subfc r3,r10,r11
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10001c: 7c 80 01 14 adde r4,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_subfc_4>:
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100024: 7c 6a 58 10 subfc r3,r10,r11
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100028: 7c 80 01 14 adde r4,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_subfc_5>:
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100030: 7c 6a 58 10 subfc r3,r10,r11
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100034: 7c 80 01 14 adde r4,r0,r0
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100038: 4e 80 00 20 blr
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@ -0,0 +1,5 @@
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0000000000000000 t test_subfc_1
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000000000000000c t test_subfc_2
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0000000000000018 t test_subfc_3
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0000000000000024 t test_subfc_4
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0000000000000030 t test_subfc_5
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Binary file not shown.
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@ -4,22 +4,27 @@
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Disassembly of section .text:
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0000000000100000 <test_subfe>:
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0000000000100000 <test_subfe_1>:
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100000: 7c 6a 59 10 subfe r3,r10,r11
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100004: 4e 80 00 20 blr
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100004: 7c 80 01 14 adde r4,r0,r0
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100008: 4e 80 00 20 blr
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0000000000100008 <test_subfe_2>:
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100008: 7c 6a 59 10 subfe r3,r10,r11
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_subfe_3>:
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100010: 7c 6a 59 10 subfe r3,r10,r11
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000000000010000c <test_subfe_2>:
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10000c: 7c 6a 59 10 subfe r3,r10,r11
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100010: 7c 80 01 14 adde r4,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_subfe_4>:
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0000000000100018 <test_subfe_3>:
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100018: 7c 6a 59 10 subfe r3,r10,r11
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10001c: 4e 80 00 20 blr
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10001c: 7c 80 01 14 adde r4,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100020 <test_subfe_5>:
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100020: 7c 6a 59 10 subfe r3,r10,r11
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100024: 4e 80 00 20 blr
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0000000000100024 <test_subfe_4>:
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100024: 7c 6a 59 10 subfe r3,r10,r11
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100028: 7c 80 01 14 adde r4,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_subfe_5>:
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100030: 7c 6a 59 10 subfe r3,r10,r11
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100034: 7c 80 01 14 adde r4,r0,r0
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100038: 4e 80 00 20 blr
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@ -1,5 +1,5 @@
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0000000000000000 t test_subfe
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0000000000000008 t test_subfe_2
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0000000000000010 t test_subfe_3
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0000000000000018 t test_subfe_4
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0000000000000020 t test_subfe_5
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0000000000000000 t test_subfe_1
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000000000000000c t test_subfe_2
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0000000000000018 t test_subfe_3
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0000000000000024 t test_subfe_4
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0000000000000030 t test_subfe_5
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfic.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_subfic_1>:
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100000: 20 6a 03 c0 subfic r3,r10,960
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100004: 7c 80 01 14 adde r4,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_subfic_2>:
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10000c: 20 6a ff 16 subfic r3,r10,-234
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100010: 7c 80 01 14 adde r4,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_subfic_3>:
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100018: 20 6a 00 00 subfic r3,r10,0
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10001c: 7c 80 01 14 adde r4,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_subfic_4>:
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100024: 20 6a 00 00 subfic r3,r10,0
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100028: 7c 80 01 14 adde r4,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_subfic_5>:
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100030: 20 6a 00 01 subfic r3,r10,1
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100034: 7c 80 01 14 adde r4,r0,r0
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100038: 4e 80 00 20 blr
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000000000010003c <test_subfic_6>:
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10003c: 20 6a ff ff subfic r3,r10,-1
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100040: 7c 80 01 14 adde r4,r0,r0
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100044: 4e 80 00 20 blr
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@ -0,0 +1,6 @@
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0000000000000000 t test_subfic_1
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000000000000000c t test_subfic_2
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0000000000000018 t test_subfic_3
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0000000000000024 t test_subfic_4
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0000000000000030 t test_subfic_5
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000000000000003c t test_subfic_6
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfme.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_subfme_one_ca_1>:
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100000: 7c 63 1a 78 xor r3,r3,r3
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100004: 7c 63 18 f8 not r3,r3
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100008: 30 63 00 01 addic r3,r3,1
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10000c: 7c 6a 01 d0 subfme r3,r10
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100010: 7c 80 01 14 adde r4,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_subfme_one_ca_2>:
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100018: 7c 63 1a 78 xor r3,r3,r3
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10001c: 7c 63 18 f8 not r3,r3
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100020: 30 63 00 01 addic r3,r3,1
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100024: 7c 6a 01 d0 subfme r3,r10
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100028: 7c 80 01 14 adde r4,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_subfme_one_ca_3>:
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100030: 7c 63 1a 78 xor r3,r3,r3
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100034: 7c 63 18 f8 not r3,r3
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100038: 30 63 00 01 addic r3,r3,1
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10003c: 7c 6a 01 d0 subfme r3,r10
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100040: 7c 80 01 14 adde r4,r0,r0
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100044: 4e 80 00 20 blr
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0000000000100048 <test_subfme_one_ca_4>:
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100048: 7c 63 1a 78 xor r3,r3,r3
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10004c: 7c 63 18 f8 not r3,r3
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100050: 30 63 00 01 addic r3,r3,1
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100054: 7c 6a 01 d0 subfme r3,r10
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100058: 7c 80 01 14 adde r4,r0,r0
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10005c: 4e 80 00 20 blr
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0000000000100060 <test_subfme_zero_ca_1>:
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100060: 7c 63 1a 78 xor r3,r3,r3
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100064: 30 63 00 01 addic r3,r3,1
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100068: 7c 6a 01 d0 subfme r3,r10
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10006c: 7c 80 01 14 adde r4,r0,r0
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100070: 4e 80 00 20 blr
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0000000000100074 <test_subfme_zero_ca_2>:
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100074: 7c 63 1a 78 xor r3,r3,r3
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100078: 30 63 00 01 addic r3,r3,1
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10007c: 7c 6a 01 d0 subfme r3,r10
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100080: 7c 80 01 14 adde r4,r0,r0
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100084: 4e 80 00 20 blr
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0000000000100088 <test_subfme_zero_ca_3>:
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100088: 7c 63 1a 78 xor r3,r3,r3
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10008c: 30 63 00 01 addic r3,r3,1
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100090: 7c 6a 01 d0 subfme r3,r10
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100094: 7c 80 01 14 adde r4,r0,r0
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100098: 4e 80 00 20 blr
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000000000010009c <test_subfme_zero_ca_4>:
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10009c: 7c 63 1a 78 xor r3,r3,r3
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1000a0: 30 63 00 01 addic r3,r3,1
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1000a4: 7c 6a 01 d0 subfme r3,r10
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1000a8: 7c 80 01 14 adde r4,r0,r0
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1000ac: 4e 80 00 20 blr
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@ -0,0 +1,8 @@
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0000000000000000 t test_subfme_one_ca_1
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0000000000000018 t test_subfme_one_ca_2
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0000000000000030 t test_subfme_one_ca_3
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0000000000000048 t test_subfme_one_ca_4
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0000000000000060 t test_subfme_zero_ca_1
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0000000000000074 t test_subfme_zero_ca_2
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0000000000000088 t test_subfme_zero_ca_3
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000000000000009c t test_subfme_zero_ca_4
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Binary file not shown.
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_subfze.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_subfze_one_ca_1>:
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100000: 7c 63 1a 78 xor r3,r3,r3
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100004: 7c 63 18 f8 not r3,r3
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100008: 30 63 00 01 addic r3,r3,1
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10000c: 7c 6a 01 90 subfze r3,r10
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100010: 7c 80 01 14 adde r4,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_subfze_one_ca_2>:
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100018: 7c 63 1a 78 xor r3,r3,r3
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10001c: 7c 63 18 f8 not r3,r3
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100020: 30 63 00 01 addic r3,r3,1
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100024: 7c 6a 01 90 subfze r3,r10
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100028: 7c 80 01 14 adde r4,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_subfze_one_ca_3>:
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100030: 7c 63 1a 78 xor r3,r3,r3
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100034: 7c 63 18 f8 not r3,r3
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100038: 30 63 00 01 addic r3,r3,1
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10003c: 7c 6a 01 90 subfze r3,r10
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100040: 7c 80 01 14 adde r4,r0,r0
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100044: 4e 80 00 20 blr
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0000000000100048 <test_subfze_one_ca_4>:
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100048: 7c 63 1a 78 xor r3,r3,r3
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10004c: 7c 63 18 f8 not r3,r3
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100050: 30 63 00 01 addic r3,r3,1
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100054: 7c 6a 01 90 subfze r3,r10
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100058: 7c 80 01 14 adde r4,r0,r0
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10005c: 4e 80 00 20 blr
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0000000000100060 <test_subfze_zero_ca_1>:
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100060: 7c 63 1a 78 xor r3,r3,r3
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100064: 30 63 00 01 addic r3,r3,1
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100068: 7c 6a 01 90 subfze r3,r10
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10006c: 7c 80 01 14 adde r4,r0,r0
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100070: 4e 80 00 20 blr
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0000000000100074 <test_subfze_zero_ca_2>:
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100074: 7c 63 1a 78 xor r3,r3,r3
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100078: 30 63 00 01 addic r3,r3,1
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10007c: 7c 6a 01 90 subfze r3,r10
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100080: 7c 80 01 14 adde r4,r0,r0
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100084: 4e 80 00 20 blr
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0000000000100088 <test_subfze_zero_ca_3>:
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100088: 7c 63 1a 78 xor r3,r3,r3
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10008c: 30 63 00 01 addic r3,r3,1
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100090: 7c 6a 01 90 subfze r3,r10
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100094: 7c 80 01 14 adde r4,r0,r0
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100098: 4e 80 00 20 blr
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000000000010009c <test_subfze_zero_ca_4>:
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10009c: 7c 63 1a 78 xor r3,r3,r3
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1000a0: 30 63 00 01 addic r3,r3,1
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1000a4: 7c 6a 01 90 subfze r3,r10
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1000a8: 7c 80 01 14 adde r4,r0,r0
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1000ac: 4e 80 00 20 blr
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@ -0,0 +1,8 @@
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0000000000000000 t test_subfze_one_ca_1
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0000000000000018 t test_subfze_one_ca_2
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0000000000000030 t test_subfze_one_ca_3
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0000000000000048 t test_subfze_one_ca_4
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0000000000000060 t test_subfze_zero_ca_1
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0000000000000074 t test_subfze_zero_ca_2
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0000000000000088 t test_subfze_zero_ca_3
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000000000000009c t test_subfze_zero_ca_4
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test_subf_1:
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#_ REGISTER_IN r10 0x00000000000103BF
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#_ REGISTER_IN r11 0x00000000000103C0
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subf r3, r10, r11
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blr
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#_ REGISTER_OUT r10 0x00000000000103BF
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#_ REGISTER_OUT r11 0x00000000000103C0
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#_ REGISTER_OUT r3 0x1
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test_subf_2:
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#_ REGISTER_IN r10 0
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#_ REGISTER_IN r11 0
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subf r3, r10, r11
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blr
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#_ REGISTER_OUT r10 0
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#_ REGISTER_OUT r11 0
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#_ REGISTER_OUT r3 0
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test_subf_3:
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#_ REGISTER_IN r10 1
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#_ REGISTER_IN r11 0
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subf r3, r10, r11
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blr
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#_ REGISTER_OUT r10 1
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#_ REGISTER_OUT r11 0
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#_ REGISTER_OUT r3 -1
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test_subf_4:
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#_ REGISTER_IN r10 0
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#_ REGISTER_IN r11 1
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subf r3, r10, r11
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blr
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#_ REGISTER_OUT r10 0
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#_ REGISTER_OUT r11 1
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#_ REGISTER_OUT r3 1
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test_subf_5:
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#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
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subf r3, r10, r11
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blr
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#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r3 0x0
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test_subfc_1:
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#_ REGISTER_IN r10 0x00000000000103BF
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#_ REGISTER_IN r11 0x00000000000103C0
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subfc r3, r10, r11
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adde r4, r0, r0
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blr
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#_ REGISTER_OUT r10 0x00000000000103BF
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#_ REGISTER_OUT r11 0x00000000000103C0
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 1
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test_subfc_2:
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#_ REGISTER_IN r10 0
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#_ REGISTER_IN r11 0
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subfc r3, r10, r11
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adde r4, r0, r0
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blr
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#_ REGISTER_OUT r10 0
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#_ REGISTER_OUT r11 0
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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test_subfc_3:
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#_ REGISTER_IN r10 1
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#_ REGISTER_IN r11 0
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subfc r3, r10, r11
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adde r4, r0, r0
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blr
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#_ REGISTER_OUT r10 1
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#_ REGISTER_OUT r11 0
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_subfc_4:
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#_ REGISTER_IN r10 0
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#_ REGISTER_IN r11 1
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subfc r3, r10, r11
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r11 1
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfc_5:
|
||||
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
|
||||
subfc r3, r10, r11
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
|
@ -1,44 +1,54 @@
|
|||
test_subfe:
|
||||
test_subfe_1:
|
||||
#_ REGISTER_IN r10 0x00000000000103BF
|
||||
#_ REGISTER_IN r11 0x00000000000103C0
|
||||
subfe r3, r10, r11
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0x00000000000103BF
|
||||
#_ REGISTER_OUT r11 0x00000000000103C0
|
||||
#_ REGISTER_OUT r3 0x0
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfe_2:
|
||||
#_ REGISTER_IN r10 0
|
||||
#_ REGISTER_IN r11 0
|
||||
subfe r3, r10, r11
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r11 0
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfe_3:
|
||||
#_ REGISTER_IN r10 1
|
||||
#_ REGISTER_IN r11 0
|
||||
subfe r3, r10, r11
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 1
|
||||
#_ REGISTER_OUT r11 0
|
||||
#_ REGISTER_OUT r3 -1
|
||||
#_ REGISTER_OUT r3 0xfffffffffffffffe
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfe_4:
|
||||
#_ REGISTER_IN r10 0
|
||||
#_ REGISTER_IN r11 1
|
||||
subfe r3, r10, r11
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r11 1
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfe_5:
|
||||
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
|
||||
subfe r3, r10, r11
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r3 0x0
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
test_subfic_1:
|
||||
#_ REGISTER_IN r10 0x00000000000103BF
|
||||
subfic r3, r10, 0x3C0
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0x00000000000103BF
|
||||
#_ REGISTER_OUT r3 0xffffffffffff0001
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfic_2:
|
||||
#_ REGISTER_IN r10 0x00000000000103BF
|
||||
subfic r3, r10, -234
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0x00000000000103BF
|
||||
#_ REGISTER_OUT r3 0xfffffffffffefb57
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfic_3:
|
||||
#_ REGISTER_IN r10 0
|
||||
subfic r3, r10, 0
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfic_4:
|
||||
#_ REGISTER_IN r10 1
|
||||
subfic r3, r10, 0
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 1
|
||||
#_ REGISTER_OUT r3 -1
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfic_5:
|
||||
#_ REGISTER_IN r10 0
|
||||
subfic r3, r10, 1
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfic_6:
|
||||
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
|
||||
subfic r3, r10, -1
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
test_subfme_one_ca_1:
|
||||
#_ REGISTER_IN r10 0x00000000000103BF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0x00000000000103BF
|
||||
#_ REGISTER_OUT r3 0xfffffffffffefc40
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfme_one_ca_2:
|
||||
#_ REGISTER_IN r10 0
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r3 -1
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfme_one_ca_3:
|
||||
#_ REGISTER_IN r10 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 1
|
||||
#_ REGISTER_OUT r3 0xfffffffffffffffe
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfme_one_ca_4:
|
||||
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfme_zero_ca_1:
|
||||
#_ REGISTER_IN r10 0x00000000000103BF
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0x00000000000103BF
|
||||
#_ REGISTER_OUT r3 0xfffffffffffefc3f
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfme_zero_ca_2:
|
||||
#_ REGISTER_IN r10 0
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r3 0xfffffffffffffffe
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfme_zero_ca_3:
|
||||
#_ REGISTER_IN r10 1
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 1
|
||||
#_ REGISTER_OUT r3 0xfffffffffffffffd
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfme_zero_ca_4:
|
||||
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfme r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
test_subfze_one_ca_1:
|
||||
#_ REGISTER_IN r10 0x00000000000103BF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0x00000000000103BF
|
||||
#_ REGISTER_OUT r3 0xfffffffffffefc41
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfze_one_ca_2:
|
||||
#_ REGISTER_IN r10 0
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
|
||||
test_subfze_one_ca_3:
|
||||
#_ REGISTER_IN r10 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 1
|
||||
#_ REGISTER_OUT r3 -1
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfze_one_ca_4:
|
||||
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r3 0x1
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfze_zero_ca_1:
|
||||
#_ REGISTER_IN r10 0x00000000000103BF
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0x00000000000103BF
|
||||
#_ REGISTER_OUT r3 0xfffffffffffefc40
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfze_zero_ca_2:
|
||||
#_ REGISTER_IN r10 0
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0
|
||||
#_ REGISTER_OUT r3 0xffffffffffffffff
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfze_zero_ca_3:
|
||||
#_ REGISTER_IN r10 1
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 1
|
||||
#_ REGISTER_OUT r3 0xfffffffffffffffe
|
||||
#_ REGISTER_OUT r4 0
|
||||
|
||||
test_subfze_zero_ca_4:
|
||||
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
addic r3, r3, 1
|
||||
subfze r3, r10
|
||||
adde r4, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0
|
||||
Loading…
Reference in New Issue