diff --git a/src/xenia/cpu/testing/vector_shl_test.cc b/src/xenia/cpu/testing/vector_shl_test.cc
index cdf61c4f8..bb821edca 100644
--- a/src/xenia/cpu/testing/vector_shl_test.cc
+++ b/src/xenia/cpu/testing/vector_shl_test.cc
@@ -58,6 +58,28 @@ TEST_CASE("VECTOR_SHL_I8_CONSTANT", "[instr]") {
       });
 }
 
+// This targets the "all_same" optimization of the Int8 specialization of
+// VECTOR_SHL_V128
+TEST_CASE("VECTOR_SHL_I8_SAME_CONSTANT", "[instr]") {
+  TestFunction test([](HIRBuilder& b) {
+    StoreVR(
+        b, 3,
+        b.VectorShl(LoadVR(b, 4), b.LoadConstantVec128(vec128b(5)), INT8_TYPE));
+    b.Return();
+  });
+  test.Run(
+      [](PPCContext* ctx) {
+        ctx->v[4] = vec128b(0x7E, 0x7E, 0x7E, 0x7F, 0x80, 0xFF, 0x01, 0x12,
+                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+      },
+      [](PPCContext* ctx) {
+        auto result = ctx->v[3];
+        REQUIRE(result == vec128b(0xC0, 0xC0, 0xC0, 0xE0, 0x00, 0xE0, 0x20,
+                                  0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                  0x00, 0x00));
+      });
+}
+
 TEST_CASE("VECTOR_SHL_I16", "[instr]") {
   TestFunction test([](HIRBuilder& b) {
     StoreVR(b, 3, b.VectorShl(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE));
diff --git a/src/xenia/cpu/testing/vector_shr_test.cc b/src/xenia/cpu/testing/vector_shr_test.cc
index 8ee36ce73..000b0234e 100644
--- a/src/xenia/cpu/testing/vector_shr_test.cc
+++ b/src/xenia/cpu/testing/vector_shr_test.cc
@@ -58,6 +58,28 @@ TEST_CASE("VECTOR_SHR_I8_CONSTANT", "[instr]") {
       });
 }
 
+// This targets the "all_same" optimization of the Int8 specialization of
+// VECTOR_SHR_V128
+TEST_CASE("VECTOR_SHR_I8_SAME_CONSTANT", "[instr]") {
+  TestFunction test([](HIRBuilder& b) {
+    StoreVR(
+        b, 3,
+        b.VectorShr(LoadVR(b, 4), b.LoadConstantVec128(vec128b(3)), INT8_TYPE));
+    b.Return();
+  });
+  test.Run(
+      [](PPCContext* ctx) {
+        ctx->v[4] = vec128b(0x7E, 0x7E, 0x7E, 0x7F, 0x80, 0xFF, 0x01, 0x12,
+                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+      },
+      [](PPCContext* ctx) {
+        auto result = ctx->v[3];
+        REQUIRE(result == vec128b(0x0F, 0x0F, 0x0F, 0x0F, 0x10, 0x1F, 0x00,
+                                  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                  0x00, 0x00));
+      });
+}
+
 TEST_CASE("VECTOR_SHR_I16", "[instr]") {
   TestFunction test([](HIRBuilder& b) {
     StoreVR(b, 3, b.VectorShr(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE));